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    Method of making strained channel CMOS transistors having lattice-mismatched epitaxial
    5.
    发明授权
    Method of making strained channel CMOS transistors having lattice-mismatched epitaxial 有权
    制造具有晶格失配外延的应变通道CMOS晶体管的方法

    公开(公告)号：US07297583B2

    公开(公告)日：2007-11-20

    申请号：US11052675

    申请日：2005-02-07

    申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer O. Dokumaci ,  Haining S. Yang

    发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer O. Dokumaci ,  Haining S. Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

    摘要： A method is provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a first single-crystal semiconductor region having a first composition. A stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a single-crystal semiconductor layer having a second composition such that the single-crystal semiconductor layer is lattice-mismatched to the first region. The semiconductor layer is formed over the source and drain regions and optionally over the extension regions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or the semiconductor layer having the second composition is not formed at all in the NFET.

    摘要翻译： 提供一种方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在具有第一组成的第一单晶半导体区域中的沟道区。 应力以第一幅度施加到PFET的沟道区，但不以该尺寸施加到NFET的沟道区。 应力由具有第二组成的单晶半导体层施加使得单晶半导体层与第一区域晶格失配。 半导体层形成在源极和漏极区域上，并且任选地在距离PFET的沟道区第一距离处的PFET的延伸区域上方形成，并且形成在NFET的源极和漏极区域之上，距离 NFET的沟道区域或具有第二组成的半导体层完全不形成在NFET中。

    MOSFET structure with high mechanical stress in the channel
    7.
    发明授权
    MOSFET structure with high mechanical stress in the channel 有权
    MOSFET结构在通道中具有高机械应力

    公开(公告)号：US07002209B2

    公开(公告)日：2006-02-21

    申请号：US10851830

    申请日：2004-05-21

    申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

    摘要翻译： 本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力 。 在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。 本发明还提供了形成上述半导体器件的方法。

    FINFET SRAM WITH ASYMMETRIC GATE AND METHOD OF MANUFACTURE THEREOF
    8.
    发明申请
    FINFET SRAM WITH ASYMMETRIC GATE AND METHOD OF MANUFACTURE THEREOF 有权
    具有不对称栅的FINFET SRAM及其制造方法

    公开(公告)号：US20090014798A1

    公开(公告)日：2009-01-15

    申请号：US11776118

    申请日：2007-07-11

    申请人： Huilong Zhu ,  Haining S. Yang

    发明人： Huilong Zhu ,  Haining S. Yang

    IPC分类号： H01L21/84 ,  H01L27/12

    CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/785

    摘要： A FinFET SRAM transistor device includes transistors formed on fins with each transistor including a semiconductor channel region within a fin plus a source region and a drain region extending within the fin from opposite sides of the channel region with fin sidewalls having a gate dielectric formed thereon. Bilateral transistor gates extend from the gate dielectric. An asymmetrically doped FinFET transistor has source/drain regions doped with a first dopant type, but the asymmetrically doped FinFET transistor include at least one of the bilateral transistor gate electrode regions on one side of at least one of the fins counterdoped with respect to the first dopant type. The finFET transistors are connected in a six transistor SRAM circuit including two PFET pull-up transistors, two NFET pull down transistors and two NFET passgate transistors.

    摘要翻译： FinFET SRAM晶体管器件包括形成在鳍片上的晶体管，其中每个晶体管包括翅片内的半导体沟道区域加上源极区域和从沟道区域的相对侧在鳍片内延伸的漏极区域，其鳍状侧壁形成有栅极电介质。 双极晶体管栅极从栅极电介质延伸。 非对称掺杂的FinFET晶体管具有掺杂有第一掺杂剂类型的源极/漏极区域，但是非对称掺杂的FinFET晶体管包括至少一个鳍片的至少一个鳍片上的至少一个侧面的双侧晶体管栅极电极区域相对于第一掺杂剂 掺杂剂类型。 finFET晶体管连接在包括两个PFET上拉晶体管，两个NFET下拉晶体管和两个NFET通道晶体管的六晶体管SRAM电路中。

    Method and apparatus for increase strain effect in a transistor channel
    9.
    发明授权
    Method and apparatus for increase strain effect in a transistor channel 有权
    在晶体管通道中增加应变效应的方法和装置

    公开(公告)号：US07790558B2

    公开(公告)日：2010-09-07

    申请号：US11465663

    申请日：2006-08-18

    申请人： Haining S. Yang ,  Huilong Zhu

    发明人： Haining S. Yang ,  Huilong Zhu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L29/66545 ,  H01L29/7842

    摘要： Method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate. The method utilizes depositing a nitride film along a surface of the substrate and the gate stack. The nitride film is thicker over a surface of the substrate and thinner over a portion of the gate stack.

    摘要翻译： 在具有设置在基板上的栅极堆叠的半导体器件中增强应力的方法。 该方法利用沿着衬底的表面和栅叠层沉积氮化物膜。 氮化物膜在衬底的表面上更厚，并且在栅极堆叠的一部分上更薄。

    CMOS gate conductor having cross-diffusion barrier
    10.
    发明授权
    CMOS gate conductor having cross-diffusion barrier 有权
    CMOS栅极导体具有交叉扩散势垒

    公开(公告)号：US07528451B2

    公开(公告)日：2009-05-05

    申请号：US11692402

    申请日：2007-03-28

    申请人： Huilong Zhu ,  Thomas W. Dyer ,  Haining S. Yang

    发明人： Huilong Zhu ,  Thomas W. Dyer ,  Haining S. Yang

    IPC分类号： H01L29/76

    CPC分类号： H01L21/28044 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/78

    摘要： A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal.

    摘要翻译： 为包括具有NFET有源半导体区域的n型场效应晶体管（“NFET”）和具有PFET有源半导体区域的p型场效应晶体管（“PFET”）的晶体管对，提供栅极导体，其中 NFET和PFET有源半导体区域被隔离区隔开。 NFET栅极在NFET有源半导体区域上的第一方向上延伸。 PFET栅极在PFET有源半导体区域上沿第一方向延伸。 扩散势垒夹在NFET栅极和PFET栅极之间。 连续层在NFET栅极和PFET栅极上在第一方向上连续延伸。 连续层接触NFET栅极和PFET栅极的顶表面，并且连续层包括半导体，金属或包括金属的导电化合物中的至少一种。