公开(公告)号：US20050269561A1

公开(公告)日：2005-12-08

申请号：US10859736

申请日：2004-06-03

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含Si部分，衬底的含Si部分顶部的压缩层和半导体硅 层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。

公开(公告)号：US20070202639A1

公开(公告)日：2007-08-30

申请号：US11741441

申请日：2007-04-27

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：US20060108651A1

公开(公告)日：2006-05-25

申请号：US10904660

申请日：2004-11-22

申请人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

发明人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

IPC分类号： H01L29/94

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/0843 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A novel transistor structure and method for fabrication the same. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. The method for fabricating the transistor structure starts out with a planar semiconductor layer and a gate stack on top of the semiconductor layer. Then, top regions of the semiconductor layer on opposing sides of the gate stack are removed. Then, regions beneath the removed regions are doped to form lowered S/D regions of the transistor structure

摘要翻译： 一种新颖的晶体管结构及其制造方法。 新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。 用于制造晶体管结构的方法从在半导体层顶部的平面半导体层和栅叠层开始。 然后，去除栅极堆叠的相对侧上的半导体层的顶部区域。 然后，去除区域下方的区域被掺杂以形成晶体管结构的降低的S / D区域

公开(公告)号：US20070166897A1

公开(公告)日：2007-07-19

申请号：US11694373

申请日：2007-03-30

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/84

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrates a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含硅部分，衬底的含Si部分顶部的压缩层，以及半导体硅层 在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。

公开(公告)号：US20060125008A1

公开(公告)日：2006-06-15

申请号：US10905062

申请日：2004-12-14

申请人： Dureseti Chidambarrao ,  Bruce Doris ,  Oleg Gluschenkov ,  Omer Dokumaci ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Bruce Doris ,  Oleg Gluschenkov ,  Omer Dokumaci ,  Huilong Zhu

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：US20060124993A1

公开(公告)日：2006-06-15

申请号：US10905041

申请日：2004-12-13

申请人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

发明人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/1083 ,  H01L29/66795

摘要： A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.

摘要翻译： 一种新颖的晶体管结构及其制造方法。 晶体管结构包括（a）衬底和（b）衬底上的半导体区域，栅极介电区域和栅极区域，其中栅极电介质区域夹在半导体区域和栅极区域之间，其中半导体区域 通过所述栅极电介质区域与所述栅极区域电绝缘，其中所述半导体区域包括沟道区域和第一和第二源极/漏极区域，其中所述沟道区域夹在所述第一和第二源极/漏极区域之间，其中所述第一和/ 第二源极/漏极区域与栅极区域对准，其中沟道区域和栅极电介质区域（i）共享基本上垂直于衬底顶表面的界面，以及（ii）不共享任何界面表面 其基本上平行于衬底的顶表面。

公开(公告)号：US20070184621A1

公开(公告)日：2007-08-09

申请号：US11694225

申请日：2007-03-30

申请人： Dureseti Chidambarrao ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/7836 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76804 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659

摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

摘要翻译： 本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。 具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。 以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。 优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面 区。 与具有直壁栅电极和金属触点的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

公开(公告)号：US20070057334A1

公开(公告)日：2007-03-15

申请号：US11162424

申请日：2005-09-09

申请人： Dureseti Chidambarrao ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Huilong Zhu

IPC分类号： H01L29/94 ,  H01L21/3205

CPC分类号： H01L29/7836 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76804 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659

摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

摘要翻译： 本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。 具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。 以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。 优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面 区。 与具有直壁栅电极和金属接触的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

公开(公告)号：US07312134B2

公开(公告)日：2007-12-25

申请号：US11741441

申请日：2007-04-27

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：US07732288B2

公开(公告)日：2010-06-08

申请号：US12367764

申请日：2009-02-09

申请人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Oleg Gluschenkov ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

发明人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Oleg Gluschenkov ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L29/0843 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.

摘要翻译： 一种半导体结构的制造方法。 新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。 提供半导体层上的半导体层和栅极堆叠。 半导体层包括（i）栅极叠层正下方的沟道区，以及（ii）基本上不被栅极叠层覆盖的第一和第二半导体区，并且其中沟道区设置在第一和第二半导体区之间。 去除第一和第二半导体区域。 除去去除的第一和第二半导体区域正下方的区域，以便分别形成第一和第二源极/漏极区域，使得第一和第二源极/漏极区域的顶表面在通道区域的顶表面之下。