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公开(公告)号：US09051035B2
公开(公告)日：2015-06-09
申请号：US12780473
申请日：2010-05-14
申请人： Dustin Imel , David J. Sturtevant
发明人： Dustin Imel , David J. Sturtevant
摘要： A boatlift for use with small, manual or paddle or oar powered watercraft (such as canoes and kayaks) is provided with a guide rails on either side of the boat lift, which can be utilized by a boater to propel or urge his/her watercraft onto the boatlift. In addition, that boatlift is provided with an entrance/exit assist member which can be used by boaters with impaired leg function to enter and exit from the watercraft. The boatlift can be provided with a bench system which enables disabled persons to more easily enter and exit from small watercraft supported by the boatlift.
摘要翻译： 与小型手动或桨式或桨式船只（如独木舟和皮划艇）一起使用的船只提供在船升降机两侧的导轨，可由船员推动或推动他/她的船只 到船上 此外，该船只具有入口/出口辅助构件，该入口/出口辅助构件可以由腿部功能受损的船员使用以进入和离开船只。 船只可以设有一个台架系统，使残疾人能够更容易地进入和离开由船只支撑的小型船只。
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公开(公告)号：US20100247243A1
公开(公告)日：2010-09-30
申请号：US12780473
申请日：2010-05-14
申请人： Dustin Imel , David J. Sturtevant
发明人： Dustin Imel , David J. Sturtevant
摘要： A boatlift for use with small, manual or paddle or oar powered watercraft (such as canoes and kayaks) is provided with a guide rails on either side of the boat lift, which can be utilized by a boater to propel or urge his/her watercraft onto the boatlift. In addition, that boatlift is provided with an entrance/exit assist member which can be used by boaters with impaired leg function to enter and exit from the watercraft. The boatlift can be provided with a bench system which enables disabled persons to more easily enter and exit from small watercraft supported by the boatlift.
摘要翻译： 与小型手动或桨式或桨式船只（如独木舟和皮划艇）一起使用的船只提供在船升降机两侧的导轨，可由船员推动或推动他/她的船只 到船上 此外，该船只具有入口/出口辅助构件，该入口/出口辅助构件可以由腿部功能受损的船员使用以进入和离开船只。 船只可以设有一个台架系统，使残疾人能够更容易地进入和离开由船只支撑的小型船只。
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公开(公告)号：US20100067985A1
公开(公告)日：2010-03-18
申请号：US12557278
申请日：2009-09-10
申请人： Dustin Imel , David J. Sturtevant
发明人： Dustin Imel , David J. Sturtevant
IPC分类号： B63C3/06
CPC分类号： B63C3/06
摘要： A boatlift for use with small, manual or paddle or oar powered watercraft (such as canoes and kayaks) is provided with a guide rails on either side of the boat lift, which can be utilized by a boater to propel or urge his/her watercraft onto the boatlift. In addition, that boatlift is provided with an entrance/exit assist member which can be used by boaters with impaired leg function to enter and exit from the watercraft.
摘要翻译： 与小型手动或桨式或桨式船只（如独木舟和皮划艇）一起使用的船只提供在船升降机两侧的导轨，可由船员推动或推动他/她的船只 到船上 此外，该船只具有入口/出口辅助构件，该入口/出口辅助构件可以由腿部功能受损的船员使用以进入和离开船只。
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公开(公告)号：US07638245B2
公开(公告)日：2009-12-29
申请号：US12167381
申请日：2008-07-03
CPC分类号： G03F7/70433 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.
摘要翻译： 根据第一设计制造集成电路的方法。 第一种设计是第一种模式，第一种模式是第一种设计所独有的。 使用在其上的块中形成有第一图案的第一掩模对第一图案成像。 在第一掩模上不形成第一和第二设计的其它图案。 使用在其上的块中形成有第二图案的第二掩模将第二图案成像在基板上。 在第二掩模上形成至少一个第三层图案。
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公开(公告)号：US20080274417A1
公开(公告)日：2008-11-06
申请号：US12167381
申请日：2008-07-03
IPC分类号： G03F1/00
CPC分类号： G03F7/70433 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.
摘要翻译： 根据第一设计制造集成电路的方法。 第一种设计是第一种模式，第一种模式是第一种设计所独有的。 使用在其上的块中形成有第一图案的第一掩模对第一图案成像。 在第一掩模上不形成第一和第二设计的其它图案。 使用在其上的块中形成有第二图案的第二掩模将第二图案成像在基板上。 在第二掩模上形成至少一个第三层图案。
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公开(公告)号：US20080216048A1
公开(公告)日：2008-09-04
申请号：US12117379
申请日：2008-05-08
申请人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
发明人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
摘要翻译： 衬底上集成电路的图形配置图。 图形轮廓图包括对基片上的集成电路的管芯放置边界和镜头放置边界的描绘。 还包括集成电路属性信息轮廓，其中轮廓不限于管芯放置边界或射击放置边界中的任何一个。 以这种方式，提供了用于集成电路的三个关键信息，包括集成电路属性信息，管芯放置和射击放置。 因为这三条信息以图形形式呈现，所以解释信息要容易得多。 例如，确定哪些投篮和投篮位置具有处于风险中的属性以及哪些投篮和投篮位置具有足够的财产配置文件将变得更加容易。
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公开(公告)号：US08685633B2
公开(公告)日：2014-04-01
申请号：US10929706
申请日：2004-08-30
IPC分类号： G03F1/00
CPC分类号： G03F7/70466 , G03F7/70425
摘要： A method of printing an image on a wafer. The method includes the steps of printing a main image, wherein the main image includes fields which are fully on the wafer, and printing an alternate image, wherein the alternate image includes fields which are only partially on the wafer. The alternate image could be placed on a separate mask which is loaded onto the exposure tool after the mask with the main image has completed printing. Alternatively, it could be an extra image specially inserted on the mask with the main image for that layer.
摘要翻译： 一种在晶片上打印图像的方法。 该方法包括打印主图像的步骤，其中主图像包括完全在晶片上的场，以及打印替代图像，其中替代图像包括仅部分地在晶片上的场。 替代图像可以被放置在单独的掩模上，其中主图像的掩模已经完成打印之后被加载到曝光工具上。 或者，它可以是特别插入到掩模上的额外的图像，该图像的主图像。
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公开(公告)号：US07930655B2
公开(公告)日：2011-04-19
申请号：US12117379
申请日：2008-05-08
申请人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
发明人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
摘要翻译： 衬底上集成电路的图形配置图。 图形轮廓图包括对基片上的集成电路的管芯放置边界和镜头放置边界的描绘。 还包括集成电路属性信息轮廓，其中轮廓不限于管芯放置边界或射击放置边界中的任何一个。 以这种方式，提供了用于集成电路的三个关键信息，包括集成电路属性信息，管芯放置和射击放置。 因为这三条信息以图形形式呈现，所以解释信息要容易得多。 例如，确定哪些投篮和投篮位置具有处于风险中的属性以及哪些投篮和投篮位置具有足够的财产配置文件将变得更加容易。
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公开(公告)号：US07395522B2
公开(公告)日：2008-07-01
申请号：US10801310
申请日：2004-03-16
申请人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
发明人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
摘要翻译： 衬底上集成电路的图形配置图。 图形轮廓图包括对基片上的集成电路的管芯放置边界和镜头放置边界的描绘。 还包括集成电路属性信息轮廓，其中轮廓不限于管芯放置边界或射击放置边界中的任何一个。 以这种方式，提供了用于集成电路的三个关键信息，包括集成电路属性信息，管芯放置和射击放置。 因为这三条信息以图形形式呈现，所以解释信息要容易得多。 例如，确定哪些投篮和投篮位置具有处于风险中的属性以及哪些投篮和投篮位置具有足够的财产配置文件将变得更加容易。
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公开(公告)号：US07018753B2
公开(公告)日：2006-03-28
申请号：US10429376
申请日：2003-05-05
CPC分类号： G03F7/70433 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.
摘要翻译： 一种根据第一设计制造集成电路的方法，其通过使用具有与第二设计相同的第一图案块的第一掩模成像基板上的第一层，但是没有第一或第二设计和成像的任何其它图案 第二层，使用具有第一图案独特的第二图案的块和至少一个第三图案的第二掩模。 第一图案的块在第一栅格中重复曝光，并且第二图案的块在第二栅格中重复地暴露，每个在相应层中不重叠。 栅格对齐，使得在集成电路之间的划线中的集成电路和测试结构适当地形成在衬底上。 第一种模式可以用于大字段，第二种模式可以用于小字段。
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