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Patent Agency Ranking
公开(公告)号：US20160335160A1
公开(公告)日：2016-11-17
申请号：US15107751
申请日：2014-04-03
Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Inventor： TONG ZHANG
CPC classification number: G06F11/1096 , G06F11/1012 , G06F2211/109 , G11C29/50004 , G11C2029/5004 , H03M13/1108 , H03M13/1177
Abstract: Technologies are described for systems, devices and methods effective to decode data read from a memory. Coded data may be stored in a buffer. A parity check syndrome vector may be calculated by a bit flip module, based on the coded data and based on a parity matrix. The parity check syndrome vector may include unsatisfied bits. The parity check syndrome vector may be stored in the buffer. The bit flip module may calculate a speculated bit flip threshold based on a feature of the parity matrix. The bit flip module may determine, based on the parity check syndrome vector, a number of unsatisfied parity checks participated in by a particular bit of the coded data. The bit flip module may flip the particular bit in response to the number of unsatisfied parity checks for the particular bit being greater than or equal to the speculated bit flip threshold.
Abstract translation: 描述了有效解码从存储器读取的数据的系统，设备和方法的技术。 编码数据可以存储在缓冲器中。 可以通过位翻转模块，基于编码数据并基于奇偶矩阵来计算奇偶校验校验子矢量。 奇偶校验矩阵向量可以包括不满足的比特。 奇偶校验校验子载体可以存储在缓冲器中。 位翻转模块可以基于奇偶校验矩阵的特征来计算推定的位翻转阈值。 位翻转模块可以基于奇偶校验校验子矢量确定由编码数据的特定比特参与的多个不满足的奇偶校验。 响应于特定位的不满足奇偶校验的数量大于或等于推定的位翻转阈值，位翻转模块可以翻转特定位。
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公开(公告)号：US20170269841A1
公开(公告)日：2017-09-21
申请号：US15612452
申请日：2017-06-02
Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Inventor： TONG ZHANG
CPC classification number: G06F11/1068 , G06F11/1048 , G11C29/4401 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208 , G11C2029/4402
Abstract: Technologies are generally described for systems, devices, and methods effective to operate a memory device. A memory controller may compress initial data to produce compressed data. The memory controller may select a storage block in the memory device. The memory controller may identify one or more positions of defective cells in the selected storage block. The memory controller may manipulate the compressed data based on the identified one or more positions to produce manipulated data. The memory controller may store the manipulated data in the selected storage block.
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公开(公告)号：US20160118137A1
公开(公告)日：2016-04-28
申请号：US14649505
申请日：2013-08-30
Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC
Inventor： TONG ZHANG
CPC classification number: G11C16/3495 , G06F11/073 , G06F11/076 , G06F11/0793 , G06F11/1048 , G11C7/14 , G11C16/26 , G11C16/30 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/4401 , G11C2029/0411
Abstract: Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate estimator module may estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. A voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory.
Abstract translation: 通常描述了有效降低闪存中功耗的系统，设备和方法的技术。 在一些示例中，误码率估计器模块可以估计两个或多个比特错误率。 两个或多个误码率可能与应用从存储器读取的相应电压相关联。 电压设置模块可以被配置为与误码率估计器模块通信。 电压设置模块可以被配置为选择从存储器读取的电压。 可以基于两个或多个误码率并且基于纠错水平来选择电压。 误差校正级别可以是可用于校正来自存储器的读取错误的公差级别。
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公开(公告)号：US20160283117A1
公开(公告)日：2016-09-29
申请号：US14651091
申请日：2013-12-20
Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Inventor： TONG ZHANG
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0673 , G06F11/1012 , G06F11/1068 , G11C16/349 , G11C29/12 , G11C29/52 , G11C29/70 , G11C2029/0409 , G11C2029/0411
Abstract: Technologies are generally described for systems, devices and methods effective to operate a memory device. A memory controller may compress initial data to produce compressed data. The memory controller may select a storage block in the memory device. The memory controller may identify one or more positions of defective cells in the selected storage block. The memory controller may manipulate the compressed data based on the identified one or more positions to produce manipulated data. The memory controller may store the manipulated data in the selected storage block.
Abstract translation: 通常描述了有效操作存储器件的系统，设备和方法的技术。 存储器控制器可以压缩初始数据以产生压缩数据。 存储器控制器可以选择存储器件中的存储块。 存储器控制器可以识别所选存储块中的缺陷单元的一个或多个位置。 存储器控制器可以基于所识别的一个或多个位置来操纵压缩数据以产生操纵数据。 存储器控制器可以将所操纵的数据存储在所选择的存储块中。
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公开(公告)号：US20160085624A1
公开(公告)日：2016-03-24
申请号：US14494319
申请日：2014-09-23
Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Inventor： TONG ZHANG
IPC: G06F11/10
CPC classification number: G06F11/1016 , G06F11/1048 , H04L1/0083
Abstract: Technologies are generally described for systems, devices and methods relating to generation of an instruction to store data. Read unit length information may be identified for data. The read unit length information may include a read unit length. The data may have a data length. The data length may implicate a first error correction code of a first size. The read unit length may relate to an amount of the data to be read as a unit from a memory. The read unit length may be different from the data length. A second error correction code may be determined to store the data. The second error correction code may be based on the read unit length information. The second error correction code may have a second size. The instruction may be effective to store the second error correction code in association with the data in a memory.
Abstract translation: 通常描述与生成用于存储数据的指令相关的系统，设备和方法的技术。 可以为数据识别读取单位长度信息。 读取单位长度信息可以包括读取单位长度。 数据可能具有数据长度。 数据长度可能涉及第一尺寸的第一纠错码。 读取单元长度可以与要从存储器一个单元读取的数据的量相关。 读取单位长度可能与数据长度不同。 可以确定第二纠错码来存储数据。 第二纠错码可以基于读取的单位长度信息。 第二纠错码可以具有第二大小。 该指令可以有效地将第二纠错码与存储器中的数据相关联地存储。
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