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31 条记录 (耗时 0.032 秒)

    Circuit and method of encoding and decoding digital data transmitted along optical fibers
    4.
    发明授权
    Circuit and method of encoding and decoding digital data transmitted along optical fibers 失效
    对沿光纤传输的数字数据进行编码和解码的电路和方法

    公开(公告)号：US5673130A

    公开(公告)日：1997-09-30

    申请号：US582841

    申请日：1996-01-02

    申请人： Ray D. Sundstrom ,  Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    发明人： Ray D. Sundstrom ,  Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    IPC分类号： H03M5/04 ,  H04B10/02 ,  H04B10/12 ,  H04B10/18 ,  H04L7/00 ,  H04L25/06 ,  H04L25/49 ,  H04B10/00

    CPC分类号： H04B10/516 ,  H04L25/062 ,  H04L7/0008 ,  H04L7/0075

    摘要： A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.

    摘要翻译： 数据发送器（12）将并行数据作为光脉冲发送在多个光通道（14）上。 数据接收器（16）将光脉冲转换回电压电平，并将电压电平与参考电容器电压（42）进行比较。 在检测逻辑和逻辑零时，电容电压应保持适当的噪声容限的中档值。 任何长串连续的逻辑或零都会使电容器电压与数据电压相同的电平进行充放电，从而导致数据错误。 为了防止数据错误，通过反转某些位来对数据进行编码（18）以分解长序列的连续逻辑状态。 编码信息作为发送时钟通过另一个光纤信道被发送到数据接收器。 检索解码信息（20），使得编码数据可被转换回适当的逻辑状态。

    Differential charge and dump optoelectronic receiver
    5.
    发明授权
    Differential charge and dump optoelectronic receiver 失效
    差分充放电光电接收器

    公开(公告)号：US6091531A

    公开(公告)日：2000-07-18

    申请号：US15897

    申请日：1998-01-30

    申请人： Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    发明人： Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    IPC分类号： H04B10/69 ,  H04B10/06

    CPC分类号： H04B10/695 ,  H04B10/6932

    摘要： A differential charge and dump optoelectronic receiver for baseband digital optoelectronic data links is disclosed having a preamplifier and a voltage controlled current source that defines the tail current of a differential pair functioning as a two quadrant multiplier, and using capacitors as loads on the differential pair making said differential pair an integrator. The integrator provides a full differential output, part of which is fedback to control the gain of the preamplifier. In a preferred embodiment, one integrator pair is used to recover the data from a Manchester encoded data stream. In another preferred embodiment, two pairs of integrators are used for QPSK like codes.

    摘要翻译： 公开了一种用于基带数字光电数据链路的差分充电和转储光电接收器，其具有前置放大器和电压控制电流源，其限定用作二象限乘法器的差分对的尾电流，并且使用电容器作为差分对上的负载 所述差分对是积分器。 积分器提供全差分输出，其中一部分反馈控制前置放大器的增益。 在优选实施例中，使用一个积分器对来从曼彻斯特编码数据流中恢复数据。 在另一个优选实施例中，两对积分器被用于QPSK相似代码。

    Signal processing method
    6.
    发明授权
    Signal processing method 失效
    信号处理方法

    公开(公告)号：US5703506A

    公开(公告)日：1997-12-30

    申请号：US578726

    申请日：1995-12-26

    申请人： Stephen G. Shook ,  Christopher K. Y. Chun ,  Daniel B. Schwartz

    发明人： Stephen G. Shook ,  Christopher K. Y. Chun ,  Daniel B. Schwartz

    IPC分类号： H04B10/158 ,  H04L25/06 ,  H04Q9/00 ,  G08G1/01

    CPC分类号： H04B10/697 ,  H04L25/062

    摘要： A signal processing circuit (10) performs a sample and hold (16) of an input signal (14) and stores a maximum value of the input signal (18). A guardband signal (21) is developed that is less than the maximum value that is stored. The input signal is compared to the guardband signal to determine if the input signal is above or below the guardband signal. A threshold signal (25) is developed by taking a percentage of the maximum value that is stored. The input signal is compared to the threshold signal to regenerate the input waveform. If the input signal is below the guardband signal and above the threshold signal, the sample and hold circuit is reset to acquire a new maximum value of the input signal so that a new threshold can be used for regenerating the input signal.

    摘要翻译： 信号处理电路（10）执行输入信号（14）的采样和保持（16）并存储输入信号（18）的最大值。 开发出小于存储的最大值的保护带信号（21）。 将输入信号与保护频带信号进行比较，以确定输入信号是否高于或低于保护频带信号。 通过获取存储的最大值的百分比来开发阈值信号（25）。 将输入信号与阈值信号进行比较，以重新生成输入波形。 如果输入信号低于保护带信号并且高于阈值信号，则采样和保持电路被复位以获取输入信号的新的最大值，使得可以使用新的阈值来再生输入信号。

    WIRELESS COMMUNICATION UNIT, BASEBAND MODULE, RADIO FREQUENCY MODULE, WIRELESS TERMINAL AND COMPUTER PROGRAM PRODUCT
    7.
    发明申请
    WIRELESS COMMUNICATION UNIT, BASEBAND MODULE, RADIO FREQUENCY MODULE, WIRELESS TERMINAL AND COMPUTER PROGRAM PRODUCT 有权
    无线通信单元，基带模块，无线电频率模块，无线终端和计算机程序产品

    公开(公告)号：US20100311464A1

    公开(公告)日：2010-12-09

    申请号：US12600007

    申请日：2007-05-25

    申请人： Paul Kelleher ,  Conor Okeeffe ,  Daniel B. Schwartz ,  Kevin Traylor

    发明人： Paul Kelleher ,  Conor Okeeffe ,  Daniel B. Schwartz ,  Kevin Traylor

    IPC分类号： H04M1/00

    CPC分类号： H04B1/406 ,  H03L7/1976

    摘要： A wireless communication unit has two or more communication modes including one or more mobile phone mode, in which mobile phone mode the wireless communication unit is able to transmit or receive wireless signals via an antenna from and/or to a mobile phone network in accordance with a communication protocol. The unit includes a baseband module and a radiofrequency module. A radiofrequency interface of the baseband module is connected to the radiofrequency module, for receiving and/or transmitting baseband signals from and/or to the radiofrequency module. The radiofrequency module includes a baseband interface, for receiving and/or transmitting the baseband signals to the baseband module and an antenna interface (AI) connectable to an antenna for receiving and/or transmitting radiofrequency signals from and/or to the antenna. A clock system is connected to the radiofrequency interface and the baseband interface. The clock system can provide a clock signal with a clock rate of to the radiofrequency interface and the baseband interface in one or more of the one or more mobile phone modes.

    摘要翻译： 无线通信单元具有包括一个或多个移动电话模式的两个或多个通信模式，其中移动电话模式，无线通信单元能够经由天线从移动电话网络和/或向移动电话网络发送或接收无线信号，根据 通信协议。 该单元包括基带模块和射频模块。 基带模块的射频接口连接到射频模块，用于从射频模块接收和/或发射基带信号。 射频模块包括用于接收和/或发送基带信号到基带模块的基带接口和可连接到天线的天线接口（AI），用于从天线接收和/或发射射频信号。 时钟系统连接到射频接口和基带接口。 时钟系统可以在一个或多个移动电话模式中的一个或多个中提供具有到射频接口和基带接口的时钟速率的时钟信号。

    WIRELESS COMMUNICATION DEVICE, INTEGRATED CIRCUIT AND METHOD OF TIMING SYNCHRONISATION
    8.
    发明申请
    WIRELESS COMMUNICATION DEVICE, INTEGRATED CIRCUIT AND METHOD OF TIMING SYNCHRONISATION 有权
    无线通信设备，集成电路和时序同步的方法

    公开(公告)号：US20100034192A1

    公开(公告)日：2010-02-11

    申请号：US12521862

    申请日：2007-01-02

    申请人： Norman Beamish ,  Paul Kelleher ,  Daniel B. Schwartz

    发明人： Norman Beamish ,  Paul Kelleher ,  Daniel B. Schwartz

    IPC分类号： H04J3/06

    CPC分类号： H04L7/04 ,  H04J3/0685

    摘要： A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronisation logic operably coupled to a counter, such that data is sampled by the timing synchronisation logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterised in that the timing synchronisation logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronisation. In particular, the inventive concept may allow a radio frequency integrated circuit to implement timing synchronisation by advancing or retarding an ‘actual’ signal sent from digital baseband circuits in a 3G DigRF wireless communication device.

    摘要翻译： 无线通信设备包括第一子系统，其被布置为将数据传递到第二子系统，该第二子系统包括可操作地耦合到计数器的定时同步逻辑，使得当数据被从第二子系统传送到第二子系统时由定时同步逻辑采样 第一子系统，其中所述无线通信装置的特征在于，所述定时同步逻辑被布置成确定第一数据帧的位置，并且响应于所述定时同步逻辑启动所述计数器的计数处理并且确定第二数据帧的位置 响应于此从计数器的计数处理确定计数值，并且响应于计数值确定是否对正被传递到第二子系统的数据启动定时提前或定时延迟操作。 以这种方式，本发明的概念为无线通信设备提供了实现定时同步的机制。 特别地，本发明的概念可以允许射频集成电路通过推进或延迟在3G DigRF无线通信设备中从数字基带电路发送的“实际”信号来实现定时同步。

    Wireless Receiver for removing direct current offset component
    9.
    发明申请
    Wireless Receiver for removing direct current offset component 有权
    用于去除直流偏移分量的无线接收器

    公开(公告)号：US20070280379A1

    公开(公告)日：2007-12-06

    申请号：US11443199

    申请日：2006-05-30

    申请人： Man Shing Wong ,  Daniel B. Schwartz

    发明人： Man Shing Wong ,  Daniel B. Schwartz

    IPC分类号： H04L27/22

    CPC分类号： H04L25/06 ,  H03D7/00

    摘要： A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.

    摘要翻译： 无线接收机包括硬件（HW）块，转换器块和数字信号处理器（DSP）。 HW块接收具有第一DC偏移分量（DCOC）的无线信号，去除第一DCOC的一部分以产生以DC为中心的残余DCOC，并产生估计残余DCOC的参数。 转换器块耦合到HW块并接收以DC为中心的残余DCOC，并将其转换为以IF为中心的残留DCOC。 DSP耦合到HW块和转换器模块，并从转换器模块接收以IF为中心的残留DCOC和来自HW模块的参数，并使用参数来消除残余DCOC，并生成基本信号 没有第一个DCOC和剩余的DCOC。

    Wireless communication device, integrated circuit and method of timing synchronisation
    10.
    发明授权
    Wireless communication device, integrated circuit and method of timing synchronisation 有权
    无线通信设备，集成电路和定时同步方法

    公开(公告)号：US08379627B2

    公开(公告)日：2013-02-19

    申请号：US12521862

    申请日：2007-01-02

    申请人： Norman Beamish ,  Paul Kelleher ,  Daniel B. Schwartz

    发明人： Norman Beamish ,  Paul Kelleher ,  Daniel B. Schwartz

    IPC分类号： H04J3/06 ,  H04L12/28 ,  H04L12/56

    CPC分类号： H04L7/04 ,  H04J3/0685

    摘要： A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronization logic operably coupled to a counter, such that data is sampled by the timing synchronization logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterized in that the timing synchronization logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronization. In particular, the inventive concept may allow a radio frequency integrated circuit to implement timing synchronization by advancing or retarding an ‘actual’ signal sent from digital baseband circuits in a 3G DigRF wireless communication device.

    摘要翻译： 无线通信设备包括第一子系统，其被布置为将数据传递到第二子系统，该第二子系统包括可操作地耦合到计数器的定时同步逻辑，使得当数据被从第二子系统传送到第二子系统时由定时同步逻辑采样 第一子系统，其中所述无线通信装置的特征在于，所述定时同步逻辑被布置成确定第一数据帧的位置，并且响应于所述定时同步逻辑启动所述计数器的计数处理并且确定第二数据帧的位置 响应于此从计数器的计数处理确定计数值，并且响应于计数值确定是否对正被传递到第二子系统的数据启动定时提前或定时延迟操作。 以这种方式，本发明的概念为无线通信设备提供了实现定时同步的机制。 具体地，本发明的概念可以允许射频集成电路通过推进或延迟在3G DigRF无线通信设备中从数字基带电路发送的实际信号来实现定时同步。