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59 条记录 (耗时 0.039 秒)

    Signal processing method
    5.
    发明授权
    Signal processing method 失效
    信号处理方法

    公开(公告)号：US5703506A

    公开(公告)日：1997-12-30

    申请号：US578726

    申请日：1995-12-26

    申请人： Stephen G. Shook ,  Christopher K. Y. Chun ,  Daniel B. Schwartz

    发明人： Stephen G. Shook ,  Christopher K. Y. Chun ,  Daniel B. Schwartz

    IPC分类号： H04B10/158 ,  H04L25/06 ,  H04Q9/00 ,  G08G1/01

    CPC分类号： H04B10/697 ,  H04L25/062

    摘要： A signal processing circuit (10) performs a sample and hold (16) of an input signal (14) and stores a maximum value of the input signal (18). A guardband signal (21) is developed that is less than the maximum value that is stored. The input signal is compared to the guardband signal to determine if the input signal is above or below the guardband signal. A threshold signal (25) is developed by taking a percentage of the maximum value that is stored. The input signal is compared to the threshold signal to regenerate the input waveform. If the input signal is below the guardband signal and above the threshold signal, the sample and hold circuit is reset to acquire a new maximum value of the input signal so that a new threshold can be used for regenerating the input signal.

    摘要翻译： 信号处理电路（10）执行输入信号（14）的采样和保持（16）并存储输入信号（18）的最大值。 开发出小于存储的最大值的保护带信号（21）。 将输入信号与保护频带信号进行比较，以确定输入信号是否高于或低于保护频带信号。 通过获取存储的最大值的百分比来开发阈值信号（25）。 将输入信号与阈值信号进行比较，以重新生成输入波形。 如果输入信号低于保护带信号并且高于阈值信号，则采样和保持电路被复位以获取输入信号的新的最大值，使得可以使用新的阈值来再生输入信号。

    Differential charge and dump optoelectronic receiver
    6.
    发明授权
    Differential charge and dump optoelectronic receiver 失效
    差分充放电光电接收器

    公开(公告)号：US6091531A

    公开(公告)日：2000-07-18

    申请号：US15897

    申请日：1998-01-30

    申请人： Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    发明人： Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    IPC分类号： H04B10/69 ,  H04B10/06

    CPC分类号： H04B10/695 ,  H04B10/6932

    摘要： A differential charge and dump optoelectronic receiver for baseband digital optoelectronic data links is disclosed having a preamplifier and a voltage controlled current source that defines the tail current of a differential pair functioning as a two quadrant multiplier, and using capacitors as loads on the differential pair making said differential pair an integrator. The integrator provides a full differential output, part of which is fedback to control the gain of the preamplifier. In a preferred embodiment, one integrator pair is used to recover the data from a Manchester encoded data stream. In another preferred embodiment, two pairs of integrators are used for QPSK like codes.

    摘要翻译： 公开了一种用于基带数字光电数据链路的差分充电和转储光电接收器，其具有前置放大器和电压控制电流源，其限定用作二象限乘法器的差分对的尾电流，并且使用电容器作为差分对上的负载 所述差分对是积分器。 积分器提供全差分输出，其中一部分反馈控制前置放大器的增益。 在优选实施例中，使用一个积分器对来从曼彻斯特编码数据流中恢复数据。 在另一个优选实施例中，两对积分器被用于QPSK相似代码。

    Circuit and method of encoding and decoding digital data transmitted along optical fibers
    8.
    发明授权
    Circuit and method of encoding and decoding digital data transmitted along optical fibers 失效
    对沿光纤传输的数字数据进行编码和解码的电路和方法

    公开(公告)号：US5673130A

    公开(公告)日：1997-09-30

    申请号：US582841

    申请日：1996-01-02

    申请人： Ray D. Sundstrom ,  Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    发明人： Ray D. Sundstrom ,  Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    IPC分类号： H03M5/04 ,  H04B10/02 ,  H04B10/12 ,  H04B10/18 ,  H04L7/00 ,  H04L25/06 ,  H04L25/49 ,  H04B10/00

    CPC分类号： H04B10/516 ,  H04L25/062 ,  H04L7/0008 ,  H04L7/0075

    摘要： A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.

    摘要翻译： 数据发送器（12）将并行数据作为光脉冲发送在多个光通道（14）上。 数据接收器（16）将光脉冲转换回电压电平，并将电压电平与参考电容器电压（42）进行比较。 在检测逻辑和逻辑零时，电容电压应保持适当的噪声容限的中档值。 任何长串连续的逻辑或零都会使电容器电压与数据电压相同的电平进行充放电，从而导致数据错误。 为了防止数据错误，通过反转某些位来对数据进行编码（18）以分解长序列的连续逻辑状态。 编码信息作为发送时钟通过另一个光纤信道被发送到数据接收器。 检索解码信息（20），使得编码数据可被转换回适当的逻辑状态。

    State retention power gating latch circuit
    9.
    发明授权
    State retention power gating latch circuit 有权
    状态保持电源门控锁存电路

    公开(公告)号：US07164301B2

    公开(公告)日：2007-01-16

    申请号：US11125462

    申请日：2005-05-10

    申请人： Christopher K. Y. Chun

    发明人： Christopher K. Y. Chun

    IPC分类号： H03K3/289 ,  H03K3/356

    CPC分类号： H03K3/356008 ,  H03K3/012

    摘要： A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power from the latch when the power gate signal is asserted and the latch is in a predetermined state. The method may include any one or more of pulling a node of the latch to a selected state while the power gate signal is asserted to ensure that the latch powers up in the predetermined state, providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof, switching a supply voltage to a power input of the latch based on a state of the output of the logic gate, and closing a switch to pull a node of the latch low.

    摘要翻译： 一种锁存电源的方法，包括检测锁存器的状态，检测功率门信号，在功率门信号被否定时为锁存器供电，以及当功率门信号被断言时从锁存器去除功率，并且锁存器 处于预定状态。 该方法可以包括以下任何一个或多个：将锁存器的节点拉至选定状态，同时确定电源门信号以确保锁存器在预定状态下上电，提供指示锁存状态的信号和电源门 信号到具有指示输出的逻辑门的相应输入，基于逻辑门的输出状态将电源电压切换到锁存器的电源输入，并且闭合开关以将锁存器的节点拉低。