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    Explicit skew interface for mitigating crosstalk and simultaneous switching noise
    5.
    发明授权
    Explicit skew interface for mitigating crosstalk and simultaneous switching noise 有权
    用于减轻串扰和同时开关噪声的显式偏移接口

    公开(公告)号：US08103898B2

    公开(公告)日：2012-01-24

    申请号：US11969801

    申请日：2008-01-04

    申请人： Dragos Dimitriu ,  Timothy Hollis

    发明人： Dragos Dimitriu ,  Timothy Hollis

    IPC分类号： G06F1/00 ,  H04J1/12 ,  H04J3/10

    CPC分类号： H04L7/04 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

    摘要： Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.

    摘要翻译： 公开了诸如涉及被配置为接收和处理电子数据的芯片间接口的方法和装置。 一个这样的接口包括接收机电路，其包括配置成在时钟树输入处接收时钟信号的时钟树。 时钟树分配从时钟信号延迟的多个时钟信号，使得一个或多个时钟信号具有与其它时钟信号的延迟不同的延迟。 接收机电路还包括多个数据输入锁存器，其被配置为在两个或多个不同的时间点上接收多个数据元素。 该配置至少部分地减少串扰和同时切换输出噪声。

    INPUT BUFFER WITH OPTIMAL BIASING AND METHOD THEREOF
    6.
    发明申请
    INPUT BUFFER WITH OPTIMAL BIASING AND METHOD THEREOF 有权
    输入缓冲器具有最佳偏移及其方法

    公开(公告)号：US20100231300A1

    公开(公告)日：2010-09-16

    申请号：US12787131

    申请日：2010-05-25

    申请人： Dragos Dimitriu

    发明人： Dragos Dimitriu

    IPC分类号： H03F3/45

    CPC分类号： H03K19/018528

    摘要： A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.

    摘要翻译： 描述偏置输入缓冲器的方法和电路以使输出信号的质量最大化。 输入缓冲器包括第一级，用于接收差分输入信号并产生响应于差分内部信号的平均而偏置的差分内部信号。 输入缓冲器还包括耦合到差分内部信号并被配置为产生差分输出信号的第二级。 存储器件包括具有相应输入缓冲器的存储器阵列。 接收差分输入信号，并且响应于差分内部信号的平均而产生偏置的差分内部信号。 差分输出信号在差分内部信号的第二级产生。

    Method and system for generating reference voltages for signal receivers
    8.
    发明授权
    Method and system for generating reference voltages for signal receivers 有权
    用于产生信号接收机参考电压的方法和系统

    公开(公告)号：US07577212B2

    公开(公告)日：2009-08-18

    申请号：US10930543

    申请日：2004-08-30

    申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

    发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

    IPC分类号： H03K9/00

    CPC分类号： H04L25/062

    摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

    摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。

    Input buffer with optimal biasing and method thereof
    9.
    发明授权
    Input buffer with optimal biasing and method thereof 有权
    具有最佳偏置的输入缓冲器及其方法

    公开(公告)号：US07425847B2

    公开(公告)日：2008-09-16

    申请号：US11347477

    申请日：2006-02-03

    申请人： Dragos Dimitriu

    发明人： Dragos Dimitriu

    IPC分类号： H03K19/094 ,  H03K19/0175

    CPC分类号： H03K19/018528

    摘要： A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.

    摘要翻译： 描述偏置输入缓冲器的方法和电路以使输出信号的质量最大化。 输入缓冲器包括第一级，用于接收差分输入信号并产生响应于差分内部信号的平均而偏置的差分内部信号。 输入缓冲器还包括耦合到差分内部信号并被配置为产生差分输出信号的第二级。 存储器件包括具有相应输入缓冲器的存储器阵列。 接收差分输入信号，并且响应于差分内部信号的平均而产生偏置的差分内部信号。 差分输出信号在差分内部信号的第二级产生。

    Reference Voltage Generation for Single-Ended Communication Channels
    10.
    发明申请
    Reference Voltage Generation for Single-Ended Communication Channels 有权
    单端通信信道的参考电压产生

    公开(公告)号：US20100188058A1

    公开(公告)日：2010-07-29

    申请号：US12359299

    申请日：2009-01-24

    申请人： Dragos Dimitriu ,  Timothy M. Hollis

    发明人： Dragos Dimitriu ,  Timothy M. Hollis

    IPC分类号： G05F3/00

    CPC分类号： G05F3/08 ,  H03K19/0175

    摘要： An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset. Each of these terms can be independently adjusted in first and second modes: the slope term via the voltage divider, and the offset term by the magnitude of the injected current. Use of the disclosed Vref generator in one useful implementation allows Vref to be optimized at two different values for Vddq.

    摘要翻译： 公开了一种改进的参考电压（Vref）发生器，可用于例如感​​测单端通道上的数据。 Vref发生器可以放置在包含接收器的集成电路上，或者可以放在芯片外。 在一个实施例中，Vref发生器包括与电流源组合的可调电阻分压器。 分压器参考I / O电源Vddq和Vssq，其中Vref在分压器的可调电阻之间的节点处产生。 电流源将电流注入到Vref节点中，并将其分成由分压器中使用的相同电阻器形成的不变的戴维南等效电阻。 所产生的电压等于两个项的和：包括Vref和Vddq之间的斜率的第一项，以及包括Vref偏移的第二项。 这些术语中的每一个可以在第一和第二模式中独立调整：通过分压器的斜率项，以及偏移项由注入电流的大小。 在一个有用的实现中使用所公开的Vref发生器允许在Vddq的两个不同值处优化Vref。