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    Method and circuitry for reducing duty cycle distortion in differential delay lines
    3.
    发明申请
    Method and circuitry for reducing duty cycle distortion in differential delay lines 有权
    差分延迟线减少占空比失真的方法和电路

    公开(公告)号：US20050030080A1

    公开(公告)日：2005-02-10

    申请号：US10932668

    申请日：2004-09-01

    申请人： Ronnie Harrison ,  Brent Keeth

    发明人： Ronnie Harrison ,  Brent Keeth

    IPC分类号： H03K5/00 ,  H03K5/13 ,  H03K5/156 ,  G11C8/00

    CPC分类号： H03K5/1565 ,  H03K5/133 ,  H03K2005/00208

    摘要： A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may be asymmetry associated with the physical layout of each individual delay line cell or stage, it is advantageous to cross-connect every x stage of an n-stage delay line. Method, integrated circuit, electronic system and substrate embodiments including the differential solid state delay lines are also disclosed.

    摘要翻译： 提供了一种用于减小差分固态延迟线中的占空比失真的方法和电路。 本发明的差分固态延迟线包括串联连接的多个延迟线单元或多个级。 因为可能存在与每个单独的延迟线单元或级的物理布局相关联的不对称性，所以交叉连接n级延迟线的每个x级是有利的。 还公开了包括差分固态延迟线的方法，集成电路，电子系统和衬底实施例。

    Interlaced delay-locked loolps for controlling memory-circuit timing
    4.
    发明申请
    Interlaced delay-locked loolps for controlling memory-circuit timing 失效
    用于控制存储器电路时序的隔行延迟锁定的磁带

    公开(公告)号：US20050007157A1

    公开(公告)日：2005-01-13

    申请号：US10914757

    申请日：2004-08-09

    申请人： Ronnie Harrison

    发明人： Ronnie Harrison

    IPC分类号： H03K5/13 ,  H03K5/135 ,  H03K5/26 ,  H03L7/07 ,  H03L7/081 ,  H03L7/089 ,  H03L7/10 ,  H03K5/22

    CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/135 ,  H03K5/26 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0896 ,  H03L7/10 ,  H03L2207/14

    摘要： For control, some memory circuits use a delay-locked loop to generate a set of signals, each delayed a different amount relative a reference signal. However, as circuits get faster and faster, conventional delay-locked loops require use of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal. In addition, the first and second loops are synchronized.

    摘要翻译： 为了控制，一些存储器电路使用延迟锁定环来产生一组信号，每个信号相对于参考信号延迟不同的量。 然而，随着电路越来越快，传统的延迟锁定环路需要使用额外的内插电路来产生更小的延迟，从而消耗相当大的功率和电路空间。 因此，发明人设计了一种电路，其将两个延迟锁定环交错并同步，每个延迟锁定环包括链接在一起的多个可控延迟元件。 在一个实施例中，第一循环产生相对于参考时钟信号延迟偶数个延迟周期的时钟信号序列，并且第二循环产生相对于参考时钟信号延迟奇数个延迟周期的时钟信号序列。 此外，第一和第二循环是同步的。

    Method and apparatus for generating a sequence of clock signals
    6.
    发明申请
    Method and apparatus for generating a sequence of clock signals 失效

    公开(公告)号：US20050249028A1

    公开(公告)日：2005-11-10

    申请号：US11182965

    申请日：2005-07-15

    申请人： Ronnie Harrison

    发明人： Ronnie Harrison

    IPC分类号： G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  H03L7/07 ,  H03L7/081 ,  H03L7/089

    CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0891

    摘要： A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock. As a result, all of the clock signals in the sequence generated by the delay line have respective predetermined phases relative to the phase of the command clock. One of the clock signals in the sequence is selected by a multiplexer to clock a command data latch at a time corresponding to the delay in coupling a command data bit to the latch.