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公开(公告)号：US20140063987A1
公开(公告)日：2014-03-06
申请号：US13597926
申请日：2012-08-29
IPC分类号： G11C7/00
CPC分类号： G11C29/04 , G06F13/1673 , G11C29/70 , G11C29/808 , G11C2029/0411
摘要： A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.
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公开(公告)号：US08848470B2
公开(公告)日：2014-09-30
申请号：US13597926
申请日：2012-08-29
IPC分类号： G11C29/00
CPC分类号： G11C29/04 , G06F13/1673 , G11C29/70 , G11C29/808 , G11C2029/0411
摘要： A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.
摘要翻译： 一种当存储器件之一失败时，用于继续操作包括第一和第二存储器件的存储器模块的方法和装置。 该方法包括：通过第一存储器模块接收写入操作请求以写入具有第一和第二部分的数据字。 存储器模块可以具有用于分别存储数据字的第一和第二部分的第一存储器设备和第二存储器设备。 确定第一和第二存储器件之一是否不可操作。 如果第一和第二存储器件之一不能操作，则通过将数据字的第一和第二部分写入第一和第二存储器件中的可操作的一个来执行写入操作。
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3.发明申请公开(公告)号：US20130138901A1
公开(公告)日：2013-05-30
申请号：US13307149
申请日：2011-11-30
申请人： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Anil B. Lingambudi , Girisankar Paulraj , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Anil B. Lingambudi , Girisankar Paulraj , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/16
CPC分类号： G06F11/3037 , G06F11/1658 , G06F11/1666 , G06F11/3058 , G06F2201/81
摘要： A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.
摘要翻译： 一种方法，系统和计算机程序产品实现了对系统热条件的计算机系统的存储器性能管理和增强的存储器可靠性。 当主存储器温度达到初始温度阈值时，读取将暂停到主存储器，并将读取提供给镜像存储器对中的镜像存储器，并将写入提供给主存储器和镜像存储器。 如果主存储器温度达到第二温度阈值，则对主存储器的写操作也被停止，并且主存储器通过诸如自定时刷新（STR）的DRAM省电模式被关闭，并且读取和写入被限制为 在镜像存储器对中镜像存储器。 当初级存储器温度降低到低于初始温度阈值时，通过将相干拷贝从镜像存储器写入主存储器来恢复一致性。
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4.发明授权Implementing memory performance management and enhanced memory reliability accounting for thermal conditions 有权实现内存性能管理和增强内存可靠性，以满足热条件公开(公告)号：US09442816B2
公开(公告)日：2016-09-13
申请号：US13307149
申请日：2011-11-30
申请人： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Anil B. Lingambudi , Girisankar Paulraj , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Anil B. Lingambudi , Girisankar Paulraj , Diyanesh B. Vidyapoornachary
CPC分类号： G06F11/3037 , G06F11/1658 , G06F11/1666 , G06F11/3058 , G06F2201/81
摘要： A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.
摘要翻译： 一种方法，系统和计算机程序产品实现了对系统热条件的计算机系统的存储器性能管理和增强的存储器可靠性。 当主存储器温度达到初始温度阈值时，读取将暂停到主存储器，并将读取提供给镜像存储器对中的镜像存储器，并将写入提供给主存储器和镜像存储器。 如果主存储器温度达到第二温度阈值，则对主存储器的写操作也被停止，并且主存储器通过诸如自定时刷新（STR）的DRAM省电模式被关闭，并且读取和写入被限制为 在镜像存储器对中镜像存储器。 当初级存储器温度降低到低于初始温度阈值时，通过将相干拷贝从镜像存储器写入主存储器来恢复一致性。
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公开(公告)号：US08869007B2
公开(公告)日：2014-10-21
申请号：US13523091
申请日：2012-06-14
CPC分类号： G06F11/1072 , G06F11/1048 , G11C5/04 , G11C11/40 , G11C29/4401 , G11C29/886 , G11C2029/0409 , H03M13/05
摘要： According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.
摘要翻译： 根据本发明的一个实施例，一种用于操作三维（“3D”）存储器件的方法包括由存储器控制器检测3D存储器件上的第一个错误，并由存储器控制器检测第二个错误 在3D存储器件的第一级中的第一芯片中，其中第一芯片具有相关的第一芯片选择。 该方法还包括对第二级别的第二芯片供电，从存储器控制器向3D存储器件发送命令以将第一芯片中的第一芯片替换为第二芯片，并使用错误控制代码校正第一错误 。
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公开(公告)号：US08874979B2
公开(公告)日：2014-10-28
申请号：US13523195
申请日：2012-06-14
CPC分类号： G11C29/4401 , G06F11/1048 , G06F11/1072 , G06F11/1666 , G06F11/20 , G11C7/24 , G11C29/70 , G11C29/83 , G11C2029/0411 , H03M13/05
摘要： According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips.
摘要翻译： 根据本发明的一个实施例，一种用于在三维存储器件中进行库保存的方法，该方法包括由存储器控制器检测3D存储器件中的第一个误差并检测第一个等级的第一个元件中的第二个误差 3D存储器件，其中第一级中的第一元件具有相关联的第一片选。 该方法还包括向3D存储器设备发送命令以设置3D存储器件的主逻辑部分中的模式寄存器，其使得第二元件能够接收指向第一元件的通信，并且其中第二元件处于第二等级 3D存储器件，其中第一元件和第二元件各自是包括多个芯片的存储体或存储体组。
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公开(公告)号：US20130339820A1
公开(公告)日：2013-12-19
申请号：US13523091
申请日：2012-06-14
CPC分类号： G06F11/1072 , G06F11/1048 , G11C5/04 , G11C11/40 , G11C29/4401 , G11C29/886 , G11C2029/0409 , H03M13/05
摘要： According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.
摘要翻译： 根据本发明的一个实施例，一种用于操作三维（“3D”）存储器件的方法包括由存储器控制器检测3D存储器件上的第一个错误，并由存储器控制器检测第二个错误 在3D存储器件的第一级中的第一芯片中，其中第一芯片具有相关的第一芯片选择。 该方法还包括对第二级别的第二芯片供电，从存储器控制器向3D存储器件发送命令以将第一芯片中的第一芯片替换为第二芯片，并使用错误控制代码校正第一错误 。
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公开(公告)号：US20130339821A1
公开(公告)日：2013-12-19
申请号：US13523195
申请日：2012-06-14
CPC分类号： G11C29/4401 , G06F11/1048 , G06F11/1072 , G06F11/1666 , G06F11/20 , G11C7/24 , G11C29/70 , G11C29/83 , G11C2029/0411 , H03M13/05
摘要： According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips.
摘要翻译： 根据本发明的一个实施例，一种用于在三维存储器件中进行库保存的方法，该方法包括由存储器控制器检测3D存储器件中的第一个误差并检测第一个等级的第一个元件中的第二个误差 3D存储器件，其中第一级中的第一元件具有相关联的第一片选。 该方法还包括向3D存储器设备发送命令以设置3D存储器件的主逻辑部分中的模式寄存器，其使得第二元件能够接收指向第一元件的通信，并且其中第二元件处于第二等级 3D存储器件，其中第一元件和第二元件各自是包括多个芯片的存储体或存储体组。
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9.发明授权公开(公告)号：US08930776B2
公开(公告)日：2015-01-06
申请号：US13598072
申请日：2012-08-29
IPC分类号： G06F11/00
CPC分类号： G11C29/023 , G06F11/073 , G06F11/0793 , G06F13/1689 , G11C11/40 , G11C29/028 , G11C29/44
摘要： A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.
摘要翻译： 提供了一种用于实现命令定时调整以减轻计算机系统中的动态随机存取存储器（DRAM）故障的方法，系统和计算机程序产品。 检测到预定义的DRAM故障。 响应于检测到的故障，调整一组定时器以控制用于访问DRAM的预定定时。 响应于通过调整的定时器组来解决故障，执行预定的性能水平的检查。
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10.发明授权Implementing enhanced hardware assisted DRAM repair using a data register for DRAM repair selectively provided in a DRAM module 有权在DRAM模块中选择性地提供使用用于DRAM修复的数据寄存器来实现增强的硬件辅助DRAM修复公开(公告)号：US09063902B2
公开(公告)日：2015-06-23
申请号：US13343938
申请日：2012-01-05
CPC分类号： G06F11/1666 , G06F11/1048 , G06F11/141 , G06F11/20 , G11C29/76
摘要： A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.
摘要翻译： 提供了一种在支持ECC的计算机系统中实现硬件辅助动态随机存取存储器（DRAM）修复的方法，系统和计算机程序产品。 提供DRAM修复的数据寄存器被选择性地提供在动态随机存取存储器（DRAM），存储器控制器或耦合在DRAM和存储器控制器之间的存储缓冲器之一中。 数据寄存器被配置为映射到任何地址。 响应于所检测到的配置地址，从配置的地址的读取或写入路由到数据寄存器。
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