公开(公告)号：US11719428B2

公开(公告)日：2023-08-08

申请号：US17604753

申请日：2020-04-18

Applicant: Edward B. Stoneham

Inventor： Edward B. Stoneham

IPC: F21V29/71 ,  F21V19/00 ,  F21Y115/10

CPC classification number: F21V29/717 ,  F21V19/0035 ,  F21Y2115/10

Abstract: A heat-sink assembly is configured with two parts to grip a light-emitting element and produce a transverse force urging a surface of the light-emitting element toward a surface of the heat-sink assembly, which conducts heat away from the light-emitting element. Fastening mechanisms and a fulcrum inter-connect the heat-sink parts and produce the force that grips the light-emitting element. A configuration of the heat-sink parts creates a semi-enclosed space accessible through a gap. A configuration of elastomeric gaskets within the semi-enclosed space protects a portion of the space from intrusion of liquids or other environmental influences. Configuration of the heat-sink parts to form a recess in the heat-sink assembly provides protection of the light-emitting element from mechanical damage, and the recess may contain transparent materials that further protect the light-emitting element from detrimental environmental influences.

公开(公告)号：US07411279B2

公开(公告)日：2008-08-12

申请号：US10882378

申请日：2004-06-30

Applicant: Edward B. Stoneham ,  Thomas M. Gaudette

Inventor： Edward B. Stoneham ,  Thomas M. Gaudette

IPC: H01L39/02

CPC classification number: H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/16153 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An example of a circuit structure may include a first dielectric layer having first and second surfaces, and a channel extending at least partially between the first and second surfaces and along a length of the first dielectric layer. First and second conductive layers may be disposed on respective portions of the first and second surfaces. A first conductor, having an end, may be disposed on a surface of the first dielectric layer, including at least a first portion extending around at least a portion of the conductor end. The second conductive layer may line the channel extending around a portion of the conductor end. Some examples may include a stripline having a second conductor connected to the first conductor. Some examples may include a cover having a wall positioned on the first dielectric over the second conductor.

Abstract translation: 电路结构的示例可以包括具有第一和第二表面的第一介电层以及至少部分地在第一和第二表面之间以及沿着第一介电层的长度延伸的通道。 第一和第二导电层可以设置在第一和第二表面的相应部分上。 具有端部的第一导体可以设置在第一电介质层的表面上，包括至少围绕导体端的至少一部分延伸的第一部分。 第二导电层可以围绕导体端的一部分延伸的通道线。 一些示例可以包括具有连接到第一导体的第二导体的带状线。 一些示例可以包括具有位于第二导体上的第一电介质上的壁的盖。

公开(公告)号：US5087959A

公开(公告)日：1992-02-11

申请号：US162912

申请日：1988-03-02

Applicant: Masahiro Omori ,  Edward B. Stoneham

Inventor： Masahiro Omori ,  Edward B. Stoneham

IPC: H01L23/29 ,  H01L23/31

CPC classification number: H01L23/298 ,  H01L23/3171 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/19041

Abstract: A protective coating useful as a passivation layer for semiconductor devices incorporates a thin film of an amorphous diamond-like carbon. In one implementation, a thin film of amorphous silicon is deposited over the carbon material. The semiconductive passivation coating prevents electrical shorts, dissipates charge build-up and protects against chemical contamination.

Abstract translation: 可用作半导体器件的钝化层的保护涂层结合有非晶类金刚石碳的薄膜。 在一个实施方案中，非晶硅薄膜沉积在碳材料上。 半导体钝化涂层防止电气短路，消除电荷积聚并防止化学污染。

公开(公告)号：US10568174B1

公开(公告)日：2020-02-18

申请号：US16337412

申请日：2017-10-02

Applicant: Edward B. Stoneham

Inventor： Edward B. Stoneham

IPC: H05B33/08

Abstract: A rectangular pulse generator system is operatively configured to generate a generator output signal, the generator output signal formed as a base rectangular waveform gated by a modulating rectangular waveform, the base rectangular waveform having a first frequency and the modulating rectangular waveform having a second frequency less than the first frequency. A low-pass filter coupled to the rectangular pulse generator system is configured to receive a filter input signal representative of the generator output signal and to produce a filter output signal representative of the filter input signal. A voltage-controlled current source coupled to the low-pass filter generates a drive signal conducted by at least one LED producing a light flux determined by the current level of the LED drive signal. Methods are devised for calibration and for setting the average light flux level.

公开(公告)号：US20200020382A1

公开(公告)日：2020-01-16

申请号：US16337777

申请日：2017-10-02

Applicant: Edward B. Stoneham

Inventor： Edward B. Stoneham

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4072 ,  G11C11/4099

Abstract: A digital-unit interface comprises a first node, a second node, a third node, and an amplifier assembly. The first node is connected to a pull-up resistor and is configured to be connected to the signal line of a transmission line connected to a first digital unit at a distal point. The second node is configured to be connected to a second reference electrical potential, a signal-return line of the transmission line, and a signal-return line of a second digital unit. The third node is configured to be connected to a signal line of the second digital unit. The amplifier assembly is configured to be connected between the first node and the third node and to transform between high electrical potentials on the first node and lower electrical potentials on the third node while the second digital unit communicates with the first digital unit.

公开(公告)号：US6023209A

公开(公告)日：2000-02-08

申请号：US675931

申请日：1996-07-05

Applicant: Mark V. Faulkner ,  Edward B. Stoneham ,  Clifford A. Mohwinkel ,  Mark J. Vaughan

Inventor： Mark V. Faulkner ,  Edward B. Stoneham ,  Clifford A. Mohwinkel ,  Mark J. Vaughan

IPC: H01P1/162 ,  H01P3/00 ,  H01P3/08 ,  H01L29/40 ,  H01P5/00

CPC classification number: H01L23/66 ,  H01P1/162 ,  H01P3/003 ,  H01L2223/6627 ,  H01L2924/0002

Abstract: Two or three conductor coplanar transmission lines and lossy coplanar resistive films are formed on a surface of a substrate. The resistive film dimensions and resistivity are selected to suppress various spurious electromagnetic modes within and around the substrate. The resistive films may be positioned along the outer edges of the transmission lines or between the transmission line conductors. The resistive film may have regular spaced openings for producing an average resistivity different than that of a continuous resistive film. In one embodiment, a signal conductor has a serpentine shape and resistive film elements are positioned between adjacent sections of the signal conductor. In another embodiment, interdigitated resistive film elements extend between transmission line conductors.

Abstract translation: 在基板的表面上形成两个或三个导体共面传输线和有损共面的电阻膜。 选择电阻膜尺寸和电阻率来抑制衬底内和周围的各种杂散电磁模式。 电阻膜可以沿着传输线的外边缘或传输线导体之间的位置。 电阻膜可以具有规则间隔的开口，用于产生不同于连续电阻膜的平均电阻率的平均电阻率。 在一个实施例中，信号导体具有蛇形形状，并且电阻膜元件位于信号导体的相邻部分之间。 在另一个实施例中，交错电阻膜元件在传输线导体之间延伸。

公开(公告)号：US4788156A

公开(公告)日：1988-11-29

申请号：US911270

申请日：1986-09-24

Applicant: Edward B. Stoneham ,  Masahiro Omori ,  Arthur D. Herbig

Inventor： Edward B. Stoneham ,  Masahiro Omori ,  Arthur D. Herbig

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L29/1075

Abstract: One embodiment of a process in accordance with our invention includes the step of forming a P type region on a semiconductor substrate. After the P type region is formed, an N type layer is epitaxially grown on the P type region. A Schottky gate is then formed on the N type epitaxial layer. A first portion of the epitaxial layer serves as a transistor source, a second portion of the epitaxial layer serves as the transistor drain, and a third portion of the epitaxial layer serves as the channel. Of importance, the P type semiconductor region helps prevent various short channel effects caused when current carriers flowing between the source and drain flow too far from the Schottky gate.

Abstract translation: 根据本发明的方法的一个实施方案包括在半导体衬底上形成P型区域的步骤。 在形成P型区之后，在P型区上外延生长N型层。 然后在N型外延层上形成肖特基栅极。 外延层的第一部分用作晶体管源极，外延层的第二部分用作晶体管漏极，外延层的第三部分用作沟道。 重要的是，P型半导体区域有助于防止在源极和漏极之间流动的载流子流过与肖特基栅极太远时引起的各种短沟道效应。

公开(公告)号：US07710219B2

公开(公告)日：2010-05-04

申请号：US12039536

申请日：2008-02-28

Applicant: Edward B. Stoneham

Inventor： Edward B. Stoneham

IPC: H01P5/12 ,  H03H7/46

CPC classification number: H01P1/213 ,  H01P1/2135 ,  H03D7/02

Abstract: A multiplexer circuit may include a first-frequency-quarter-wavelength transmission line extending between a junction between a common terminal and a second-frequency terminal, and a first-frequency low-impedance circuit electrically directly connecting the first transmission line to a circuit ground. In some examples, a second-frequency-quarter-wavelength transmission line may extend between the first transmission line and a third-frequency terminal. A second-frequency low-impedance circuit may electrically directly connect the second transmission line to the circuit ground. The first and second transmission lines and the first and second low-impedance circuits may provide a third-frequency transmission line. A further second-frequency low-impedance circuit may electrically couple the second terminal to the first transmission line. A third-frequency low-impedance circuit may electrically couple the second terminal to the circuit ground. The first-frequency, further second-frequency, and third-frequency low-impedance circuits and the first transmission line may provide in combination a second-frequency transmission line.

Abstract translation: 多路复用器电路可以包括在公共端子和第二频率端子之间的连接点之间延伸的第一频率四分之一波长的传输线，以及将第一传输线电连接到电路接地的第一频率低阻抗电路 。 在一些示例中，第二频率四分之一波长的传输线可以在第一传输线和第三频率终端之间延伸。 第二频率低阻抗电路可以将第二传输线电连接到电路接地。 第一和第二传输线以及第一和第二低阻抗电路可以提供第三频率传输线。 另一个第二频率低阻抗电路可以将第二端子电耦合到第一传输线。 第三频率低阻抗电路可以将第二端子电耦合到电路接地。 第一频率，第二频率和第三频率低阻抗电路和第一传输线可以组合提供第二频率传输线。

公开(公告)号：US07588966B2

公开(公告)日：2009-09-15

申请号：US12042144

申请日：2008-03-04

Applicant: Edward B. Stoneham ,  Thomas M. Gaudette

Inventor： Edward B. Stoneham ,  Thomas M. Gaudette

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L24/32 ,  H01L23/13 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuit structure may be formed in a substrate having a face and an open trench, where one or more chips are to be mounted. At least one bridge may extend across an intermediate portion of the trench, and optionally, may divide the trench into sections. A conductive adhesive layer may be applied to the substrate face and, if included, the bridge. One or more circuit chips may be mounted on the adhesive layer, with at least one edge of one circuit chip adjacent to the trench. Alternatively or additionally, an adhesive layer may be applied to a base of a chip and then mounted to the substrate face, in like fashion. The trench may accommodate excess adhesive flowing out from under the one or more chips, while the bridge retains the adhesive across the width of the trench. If the adhesive is conductive, this provides continuity of the conductive layer on the face of the substrate across the trench. In one example, pairs of circuit chips may be effectively mounted in adjacent relationship for interconnection without interference from excess adhesive.

Abstract translation: 电路结构可以形成在具有面和开放沟槽的衬底中，其中将安装一个或多个芯片。 至少一个桥可以延伸穿过沟槽的中间部分，并且可选地，可以将沟槽划分成多个部分。 可以将导电粘合剂层施加到基板表面，如果包括桥，则应用导电粘合剂层。 一个或多个电路芯片可以安装在粘合剂层上，其中一个电路芯片的至少一个边缘与沟槽相邻。 或者或另外，粘合剂层可以施加到芯片的基部，然后以类似的方式安装到基板面。 沟槽可以容纳从一个或多个芯片下面流出的多余的粘合剂，同时桥将粘合剂保持在沟槽的宽度上。 如果粘合剂是导电的，则这提供了穿过沟槽的衬底的表面上的导电层的连续性。 在一个示例中，电路芯片对可以有效地安装在相邻的关系中用于互连，而不会受到多余粘合剂的干扰。

公开(公告)号：US07119633B2

公开(公告)日：2006-10-10

申请号：US10925684

申请日：2004-08-24

Applicant: Edward B. Stoneham

Inventor： Edward B. Stoneham

IPC: H01P5/18

CPC classification number: H01P1/183

Abstract: A coupler may include four ports, and first and second sets of conductive strips. Each set of conductive strips may include a plurality of interconnected conductive strips connected between two ports. Each conductive strip of the first set may be electromagnetically coupled to a conductive strip of the second set. Conductive tabs capacitively coupled directly or indirectly to the ground conductor may extend from conductive strips of the first and second sets. An interconnection may be positioned between adjacent tabs, the interconnection connecting conductive strips of one of the sets of conductive strips. The adjacent tabs may be spaced different distances from the interconnection.