公开(公告)号：US4493023A

公开(公告)日：1985-01-08

申请号：US266403

申请日：1981-05-22

申请人： Edward S. Gavrin ,  Richard G. Bratt ,  Stephen I. Schleimer ,  John F. Pilat ,  Michael S. Richmond ,  Walter A. Wallach, Jr. ,  Richard A. Belgard ,  David A. Farber ,  John K. Ahlstrom ,  Steven J. Wallach ,  Gerald F. Clancy ,  Craig J. Mundie ,  Thomas M. Jones ,  Brett L. Bachman ,  David H. Bernstein

发明人： Edward S. Gavrin ,  Richard G. Bratt ,  Stephen I. Schleimer ,  John F. Pilat ,  Michael S. Richmond ,  Walter A. Wallach, Jr. ,  Richard A. Belgard ,  David A. Farber ,  John K. Ahlstrom ,  Steven J. Wallach ,  Gerald F. Clancy ,  Craig J. Mundie ,  Thomas M. Jones ,  Brett L. Bachman ,  David H. Bernstein

IPC分类号： G01R31/3185 ,  G06F7/00 ,  G06F7/57 ,  G06F9/22 ,  G06F9/26 ,  G06F9/35 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30

CPC分类号： G06F11/0793 ,  G01R31/318505 ,  G06F11/0721 ,  G06F11/073 ,  G06F12/0875 ,  G06F12/1483 ,  G06F7/00 ,  G06F7/483 ,  G06F9/223 ,  G06F9/226 ,  G06F9/262 ,  G06F9/268 ,  G06F9/35 ,  G06F9/4843 ,  G06F9/54 ,  G06F7/49905 ,  G06F7/4991 ,  G06F7/49926

摘要： A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

摘要翻译： 具有灵活的内部结构的数据处理系统，具有多层次的控制和堆栈机制以及执行多个并发操作的能力，并向用户提供灵活的简化界面，保护用户不受任何用户的影响。 该系统内部由多个独立的独立处理器组成，每个独立的处理器具有单独的微指令控制和至少一个独立于中央通信和存储器节点的独立端口。 通信和存储器节点是具有独立且独立的微指令控制的独立处理器，并且包括能够执行多个并发存储器和通信操作的多个独立操作的微指令控制的处理器。 寻址机制允许永久，唯一的信息识别和所有这些系统可访问和共同的极大的地址空间。 地址与系统物理配置无关。 信息被识别为细粒度级别和信息类型和格式。 保护机制提供与个体信息相关联的可变访问权限。 用户语言指令被转换为方言编码的，统一的中间级指令，以便为所有用户语言提供相同的执行功能。 操作数由统一格式名称引用，通过对用户透明的内部机制转换为地址。

公开(公告)号：US4498131A

公开(公告)日：1985-02-05

申请号：US266408

申请日：1981-05-22

申请人： Richard G. Bratt ,  Edward S. Gavrin ,  Stephen I. Schleimer ,  John F. Pilat ,  Walter A. Wallach, Jr. ,  Michael S. Richmond ,  Richard A. Belgard ,  David A. Farber ,  John K. Ahlstrom ,  Steven J. Wallach ,  Lawrence H. Katz ,  Douglas M. Wells ,  Craig J. Mundie ,  Gerald F. Clancy ,  David H. Bernstein ,  Thomas M. Jones ,  Brett L. Bachman

发明人： Richard G. Bratt ,  Edward S. Gavrin ,  Stephen I. Schleimer ,  John F. Pilat ,  Walter A. Wallach, Jr. ,  Michael S. Richmond ,  Richard A. Belgard ,  David A. Farber ,  John K. Ahlstrom ,  Steven J. Wallach ,  Lawrence H. Katz ,  Douglas M. Wells ,  Craig J. Mundie ,  Gerald F. Clancy ,  David H. Bernstein ,  Thomas M. Jones ,  Brett L. Bachman

IPC分类号： G01R31/3185 ,  G06F7/00 ,  G06F7/57 ,  G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/35 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07 ,  G06F12/08 ,  G06F12/14

CPC分类号： G01R31/318505 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/0875 ,  G06F12/1483 ,  G06F7/00 ,  G06F7/483 ,  G06F9/3013 ,  G06F9/35 ,  G06F9/4843 ,  G06F9/54 ,  G06F7/49905 ,  G06F7/4991 ,  G06F7/49926

摘要： A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system utilizes unique addressing mechanisms the addresses of which have object fields, offset fields and length fields for specifying the location and the total number of bits of an addressed object. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing the user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object.

摘要翻译： 数字数据处理系统具有被组织成至少包含操作数和指令的对象的存储器。 每个对象由识别数据处理系统和对象的唯一且永久的标识符代码来标识。 该系统利用独特的寻址机制，其地址具有用于指定寻址对象的位置和总位数的对象字段，偏移字段和长度字段。 该系统使用保护技术来防止由识别用户的主题号码，用于执行用户过程的系统的处理以及由该用户执行的系统的操作类型由用户标识的用户的未经授权的访问 用户程序。 每个对象的访问控制列表包括具有对对象的访问权限的每个对象的访问控制列表条目，以及用于在允许访问对象之前确认特定活动主体具有对特定对象的访问权限的装置。

公开(公告)号：US4675810A

公开(公告)日：1987-06-23

申请号：US266536

申请日：1981-05-22

申请人： Ronald H. Gruner ,  Gerald F. Clancy ,  Craig J. Mundie ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Richard G. Bratt ,  Edward S. Gavrin ,  Walter A. Wallach, Jr. ,  John K. Ahlstrom ,  Michael S. Richmond ,  David H. Bernstein ,  John F. Pilat ,  David A. Farber ,  Richard A. Belgard

发明人： Ronald H. Gruner ,  Gerald F. Clancy ,  Craig J. Mundie ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Richard G. Bratt ,  Edward S. Gavrin ,  Walter A. Wallach, Jr. ,  John K. Ahlstrom ,  Michael S. Richmond ,  David H. Bernstein ,  John F. Pilat ,  David A. Farber ,  Richard A. Belgard

IPC分类号： G06F9/35 ,  G06F9/42 ,  G06F9/06

CPC分类号： G06F9/4426 ,  G06F9/35

摘要： A digital computer system having a memory system organized into procedure and data objects, each having a unique identifier code and an access control list, for storing items of information and a processor for processing data in response to instructions. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in a name table which contains information from which the processor determines the location and the format for the data. The name table entry specifies a base address of one of a set thereof which change value only when a call or a return instruction is executed. A name interpretation system fetches a name table entry, calculates the base address and a displacement using the name table entry and the current architectural base address and adds the base address to the displacement to form the address of the data represented by the name.

摘要翻译： 一种数字计算机系统，其具有组织成过程和数据对象的存储器系统，每个存储器系统具有用于存储信息项的唯一标识符代码和访问控制列表，以及响应于指令处理数据的处理器。 指令包含表示数据的操作代码和名称。 每个名称对应于名称表中的名称表条目，其中包含处理器确定数据的位置和格式的信息。 名称表条目指定仅当执行呼叫或返回指令时才改变值的其中一个的基地址。 名称解释系统获取名称表项，使用名称表项和当前体系结构基地址计算基地址和位移，并将基地址添加到位移，以形成由名称表示的数据的地址。

公开(公告)号：US4498132A

公开(公告)日：1985-02-05

申请号：US266413

申请日：1981-05-22

申请人： John K. Ahlstrom ,  Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  Michael S. Richmond ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

发明人： John K. Ahlstrom ,  Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  Michael S. Richmond ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

IPC分类号： G01R31/3185 ,  G06F7/00 ,  G06F7/57 ,  G06F9/22 ,  G06F9/26 ,  G06F9/318 ,  G06F9/35 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07 ,  G06F12/08 ,  G06F12/14

CPC分类号： G06F9/54 ,  G01R31/318505 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/0875 ,  G06F12/1483 ,  G06F7/00 ,  G06F7/483 ,  G06F9/223 ,  G06F9/226 ,  G06F9/262 ,  G06F9/268 ,  G06F9/3017 ,  G06F9/35 ,  G06F9/4843 ,  G06F7/49905 ,  G06F7/4991 ,  G06F7/49926

摘要： A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system further uses multilevel microcode techniques for controlling sequences of microinstructions and for controlling the interval operations of the processor. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing a user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object. The system also includes stacks for containing information relating to the current state of execution of the system.

摘要翻译： 数字数据处理系统具有被组织成至少包含操作数和指令的对象的存储器。 每个对象由识别数据处理系统和对象的唯一且永久的标识符代码来标识。 该系统还使用多级微代码技术来控制微指令的序列并且用于控制处理器的间隔操作。 该系统使用保护技术来防止由标识用户的主题号码，用于执行用户过程的系统的处理以及由该用户执行的系统的操作类型由用户标识的用户的未经授权的访问 用户程序。 每个对象的访问控制列表包括具有对对象的访问权限的每个对象的访问控制列表条目，以及用于在允许访问对象之前确认特定活动主体具有对特定对象的访问权限的装置。 系统还包括用于包含与系统的当前执行状态有关的信息的堆栈。

公开(公告)号：US4480306A

公开(公告)日：1984-10-30

申请号：US266425

申请日：1981-05-22

申请人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

发明人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

IPC分类号： G06F9/26 ,  G06F9/22

CPC分类号： G06F9/26

摘要： A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described with reference to the invention herein, identify locations of object information to be accessed by utlizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format. Arithmetic logic unit (ALU) means, also as particularly described with reference to the invention herein, include general register means having three vertically oriented parts for storing such respective fields. Such ALU means further include an ALU microinstruction stack means having at least one microinstruction stack frame for storing the state of execution of a microinstruction. A memory microinstruction stack is provided to store a plurality of microinstruction stack frames so that microinstruction stack frames can be transferred between the ALU and the memory microinstruction stacks. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

公开(公告)号：US4514800A

公开(公告)日：1985-04-30

申请号：US266525

申请日：1981-05-22

申请人： Ronald H. Gruner ,  Gerald F. Clancy ,  Craig J. Mundie ,  Steven J. Wallach ,  Stephen I. Schleimer ,  Walter A. Wallach, Jr. ,  John K. Ahlstrom ,  David H. Bernstein ,  Michael S. Richmond ,  David A. Farber ,  John F. Pilat ,  Richard A. Belgard ,  Richard G. Bratt

发明人： Ronald H. Gruner ,  Gerald F. Clancy ,  Craig J. Mundie ,  Steven J. Wallach ,  Stephen I. Schleimer ,  Walter A. Wallach, Jr. ,  John K. Ahlstrom ,  David H. Bernstein ,  Michael S. Richmond ,  David A. Farber ,  John F. Pilat ,  Richard A. Belgard ,  Richard G. Bratt

IPC分类号： G06F9/35 ,  G06F9/40 ,  G06F13/00

CPC分类号： G06F9/4425 ,  G06F9/35

摘要： A digital computer system including a memory and a processor. The memory operates in response to memory commands received from the processor. Items of data stored in the memory include instructions to which the processor responds. Each instruction contains an operation code which belongs to one of several sets of operation codes. The meaning of a given operation code is determined by the operation code set to which the instruction belongs. Some of the instructions also contain names representing items of data used in the operation specified by the operation code. The processor includes an operation code decoding system which decodes the operation code as required for the instruction set to which it belongs, a name resolution system for deriving the address of the data item represented by a name from the name using an architectural base address contained in the name resolution system, and a control system which controls the operation of the processor. The processor performs a call operation and a return operation. Only the call operation and the return operation may change the current architectural base address. The memory further contains name table entries associated with the names. Each name table entry contains information used by the name resolution system when it resolves a name.

摘要翻译： 一种包括存储器和处理器的数字计算机系统。 存储器响应于从处理器接收的存储器命令而工作。 存储在存储器中的数据项包括处理器响应的指令。 每条指令都包含一个操作码，它属于几组操作码之一。 给定操作代码的含义由指令所属的操作代码集确定。 一些指令还包含表示由操作代码指定的操作中使用的数据项的名称。 该处理器包括操作码解码系统，该系统根据其所属的指令集的需要对操作码进行解码，一个名称解析系统，用于从名称中导出由名称所代表的数据项的地址， 名称解析系统和控制处理器的操作的控制系统。 处理器执行呼叫操作和返回操作。 只有通话操作和返回操作才能更改当前的架构基地址。 内存还包含与名称相关联的名称表条目。 每个名称表项包含名称解析系统在解析名称时使用的信息。

公开(公告)号：US4656579A

公开(公告)日：1987-04-07

申请号：US699240

申请日：1985-02-08

申请人： Brett L. Bachman ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  John F. Pilat ,  Michael S. Richmond ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr.

发明人： Brett L. Bachman ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  John F. Pilat ,  Michael S. Richmond ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr.

IPC分类号： G01R31/3185 ,  G06F7/00 ,  G06F7/57 ,  G06F9/22 ,  G06F9/26 ,  G06F9/318 ,  G06F9/35 ,  G06F9/42 ,  G06F9/44 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/14 ,  G06F9/10

CPC分类号： G06F9/4426 ,  G01R31/318505 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/0292 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/1458 ,  G06F12/1483 ,  G06F7/00 ,  G06F7/483 ,  G06F9/30192 ,  G06F9/4428 ,  G06F9/468 ,  G06F9/4843 ,  G06F9/54 ,  G06F7/49905 ,  G06F7/4991 ,  G06F7/49926

摘要： A digital computer system having a memory system organized into objects for storing items of information and a processor for processing data in response to instructions. An object identifier code is associated with each object. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions and name tables associated with the procedures. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in the name table associated with the procedure. The name table for a name contains information from which the processor may determine the location and the format for the data (e.g., an operand) represented by the name.

摘要翻译： 一种数字计算机系统，具有组织成用于存储信息项目的对象的存储器系统和用于响应于指令处理数据的处理器。 对象标识符代码与每个对象相关联。 对象包括过程对象和数据对象。 过程对象包含与过程相关联的指令和名称表的过程。 指令包含表示数据的操作代码和名称。 每个名称对应于与该过程相关联的名称表中的名称表项。 名称的名称表包含处理器可以确定由该名称表示的数据（例如，操作数）的位置和格式的信息。

公开(公告)号：US4445177A

公开(公告)日：1984-04-24

申请号：US266411

申请日：1981-05-22

申请人： Richard G. Bratt ,  Stephen I. Schleimer ,  John F. Pilat ,  Richard A. Belgard ,  Steven J. Wallach ,  Gerald F. Clancy ,  Craig J. Mundie ,  David H. Bernstein ,  Edward S. Gavrin ,  Thomas M. Jones ,  Brett L. Bachman

发明人： Richard G. Bratt ,  Stephen I. Schleimer ,  John F. Pilat ,  Richard A. Belgard ,  Steven J. Wallach ,  Gerald F. Clancy ,  Craig J. Mundie ,  David H. Bernstein ,  Edward S. Gavrin ,  Thomas M. Jones ,  Brett L. Bachman

IPC分类号： G06F9/45 ,  G06F9/22

CPC分类号： G06F8/41

摘要： A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique indentification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described withreference to the invention herein, indentify locations of object information to be accessed by utilizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format. Arithmetic logic unit (ALU) means, also as particularly described with reference to the invention herein, include general register means having three vertically oriented parts for storing such respective fields. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

公开(公告)号：US4499535A

公开(公告)日：1985-02-12

申请号：US266427

申请日：1981-05-22

申请人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Craig J. Mundie ,  James T. Nealon ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach

发明人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Craig J. Mundie ,  James T. Nealon ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach

IPC分类号： G06F9/318 ,  G06F9/34 ,  G06F7/04

CPC分类号： G06F9/30192 ,  G06F9/34

摘要： A digital computer uses a memory which is structured into objects, which are blocks of storage of arbitrary length, in which data items are accessed by descriptors which for a desired data item specify the object, the offset into that object, and the length of the data object. The computer system of the present invention further provides the ability to execute any of a plurality of dialects of internal instructions, the repertoire of such dialects being virtually infinite, since there is the ability to load a supporting microcode during operation as needed.

摘要翻译： 数字计算机使用被构造成对象的存储器，该对象是任意长度的存储块，其中通过描述符访问数据项，对于期望的数据项指定对象，到该对象的偏移量以及该对象的长度 数据对象。 本发明的计算机系统进一步提供执行内部指令的多个方言中的任何一种方式的能力，这种方言的曲目几乎是无限的，因为在需要时可以在运行期间加载支持的微代码。

公开(公告)号：US4731734A

公开(公告)日：1988-03-15

申请号：US830480

申请日：1986-02-14

申请人： Ronald H. Gruner ,  Gerald F. Clancy ,  Craig J. Mundie ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Richard G. Bratt ,  Edward S. Gavrin ,  Walter A. Wallach, Jr. ,  John K. Ahlstrom ,  Michael S. Richmond ,  David H. Bernstein

发明人： Ronald H. Gruner ,  Gerald F. Clancy ,  Craig J. Mundie ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Richard G. Bratt ,  Edward S. Gavrin ,  Walter A. Wallach, Jr. ,  John K. Ahlstrom ,  Michael S. Richmond ,  David H. Bernstein

IPC分类号： G06F9/35 ,  G06F9/44 ,  G06F9/30

CPC分类号： G06F9/4428 ,  G06F9/35

摘要： A digital computer system having a memory system organized into objects for storing data and a processor for processing data in response to instructions. An object identifier and an access control list are associated with each object. The memory system responds to logical addresses for data which specify the object containing the data and the offset of the data in the object and to a current subject for which the processor is referencing the data. The memory system performs a memory operation for the processor only if the access control list for the object specified by the logical address allows the current subject to perform the desired memory operation. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions and name tables associated with the procedures. The instructions contain operations codes and names representing data. Each name corresponds to a name table entry in the name table associated with the procedure. The name table for a name contains information from which the processor may derive the logical address for the data represented by the name. The processor may then use the logical address to specify a memory operation on the data represented by the name.

摘要翻译： 一种数字计算机系统，具有组织成用于存储数据的对象的存储器系统和用于响应于指令来处理数据的处理器。 对象标识符和访问控制列表与每个对象相关联。 存储器系统对指定包含数据的对象的数据和对象中的数据的偏移以及处理器正在引用数据的当前对象的数据进行响应。 只有当由逻辑地址指定的对象的访问控制列表允许当前主体执行所需的存储器操作时，存储器系统才对处理器执行存储器操作。 对象包括过程对象和数据对象。 过程对象包含与过程相关联的指令和名称表的过程。 指令包含表示数据的操作代码和名称。 每个名称对应于与该过程相关联的名称表中的名称表项。 名称的名称表包含信息，处理器可从中获取由该名称表示的数据的逻辑地址。 然后，处理器可以使用逻辑地址来指定对由该名称表示的数据的存储器操作。