利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.03 秒)

    Data Access Apparatus and Associated Method for Accessing Data Using Internally Generated Clocks
    1.
    发明申请
    Data Access Apparatus and Associated Method for Accessing Data Using Internally Generated Clocks 有权
    数据访问装置和使用内部生成时钟访问数据的相关方法

    公开(公告)号：US20110158005A1

    公开(公告)日：2011-06-30

    申请号：US12968719

    申请日：2010-12-15

    申请人： Eer-Wen Tyan ,  Ming-Chieh Yeh ,  Yi Ling Chen

    发明人： Eer-Wen Tyan ,  Ming-Chieh Yeh ,  Yi Ling Chen

    IPC分类号： G11C7/22 ,  G11C7/10

    CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C2207/2254

    摘要： The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data at the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.

    摘要翻译： 数据存取装置包括锁相环（PLL）和数据接收电路。 PLL提供多个内部时钟并根据相位选择信号从多个内部时钟中选择选通时钟。 数据接收电路包括锁存模块，用于根据选通时钟的触发锁存数据信号和校准电路，用于产生相位选择信号，用于在训练中的多个内部时钟处将数据与预定数据进行匹配 模式，并最终确定与在正常模式中使用的优选时钟相对应的相位选择信号。

    Data access apparatus and associated method for accessing data using internally generated clocks
    2.
    发明授权
    Data access apparatus and associated method for accessing data using internally generated clocks 有权
    数据访问装置和使用内部生成的时钟访问数据的相关方法

    公开(公告)号：US08395946B2

    公开(公告)日：2013-03-12

    申请号：US12968719

    申请日：2010-12-15

    申请人： Eer-Wen Tyan ,  Ming-Chieh Yeh ,  Yi Ling Chen

    发明人： Eer-Wen Tyan ,  Ming-Chieh Yeh ,  Yi Ling Chen

    IPC分类号： G11C7/22

    CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C2207/2254

    摘要： The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data according to the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.

    摘要翻译： 数据存取装置包括锁相环（PLL）和数据接收电路。 PLL提供多个内部时钟并根据相位选择信号从多个内部时钟中选择选通时钟。 数据接收电路包括锁存模块，用于根据选通时钟的触发锁存数据信号和校准电路，用于根据多个内部时钟产生用于使数据与预定数据匹配的相位选择信号 训练模式，最后确定对应于在正常模式中使用的优选时钟的相位选择信号。

    Apparatus and Method of Generating Universal Memory I/O
    3.
    发明申请
    Apparatus and Method of Generating Universal Memory I/O 有权
    生成通用存储器I / O的装置和方法

    公开(公告)号：US20110131354A1

    公开(公告)日：2011-06-02

    申请号：US12947966

    申请日：2010-11-17

    申请人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

    发明人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

    IPC分类号： G06F13/38

    CPC分类号： G06F17/5068

    摘要： A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

    摘要翻译： 通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。 定义模块根据多个I / O的引脚配置来定义映射表。 映射表包括多个IO和多个存储器功能之间的对应关系。 检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索对应于映射表的控制信息。 生成模块根据控制信息生成硬件描述语言（HDL）文件。 布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

    Apparatus and method of generating universal memory I/O
    4.
    发明授权
    Apparatus and method of generating universal memory I/O 有权
    产生通用存储器I / O的装置和方法

    公开(公告)号：US08635569B2

    公开(公告)日：2014-01-21

    申请号：US12947966

    申请日：2010-11-17

    申请人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

    发明人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

    摘要翻译： 通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。 定义模块根据多个I / O的引脚配置来定义映射表。 映射表包括多个IO和多个存储器功能之间的对应关系。 检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索与映射表相对应的控制信息。 生成模块根据控制信息生成硬件描述语言（HDL）文件。 布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

    I/O circuit calibration method and associated apparatus
    5.
    发明授权
    I/O circuit calibration method and associated apparatus 有权
    I / O电路校准方法及相关设备

    公开(公告)号：US08482293B2

    公开(公告)日：2013-07-09

    申请号：US12889017

    申请日：2010-09-23

    申请人： Eer-Wen Tyan ,  Ming-Chieh Yeh

    发明人： Eer-Wen Tyan ,  Ming-Chieh Yeh

    IPC分类号： G01R35/00

    CPC分类号： H04L25/029

    摘要： An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end.

    摘要翻译： 提供I / O校准方法和装置，用于校准芯片中的I / O电路的输出端的驱动阻抗。 芯片还包括多个基本阻抗和非易失性存储器。 I / O电路校准方法包括：测量一个基本阻抗的阻抗值，并将测得的阻抗值记录在非易失性存储器中; 通过选择性地传导基本阻抗来合成校准阻抗; 调整校准阻抗中传导的基本阻抗的数量，并根据测量结果估计驱动阻抗的阻抗值，并将电压除以校准阻抗和输出端的驱动阻抗。

    I/O Circuit Calibration Method and Associated Apparatus
    6.
    发明申请
    I/O Circuit Calibration Method and Associated Apparatus 有权
    I / O电路校准方法及相关设备

    公开(公告)号：US20110074520A1

    公开(公告)日：2011-03-31

    申请号：US12889017

    申请日：2010-09-23

    申请人： Eer-Wen Tyan ,  Ming-Chieh Yeh

    发明人： Eer-Wen Tyan ,  Ming-Chieh Yeh

    IPC分类号： H03H7/38

    CPC分类号： H04L25/029

    摘要： An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end.

    摘要翻译： 提供I / O校准方法和装置，用于校准芯片中的I / O电路的输出端的驱动阻抗。 芯片还包括多个基本阻抗和非易失性存储器。 I / O电路校准方法包括：测量一个基本阻抗的阻抗值，并将测得的阻抗值记录在非易失性存储器中; 通过选择性地传导基本阻抗来合成校准阻抗; 调整校准阻抗中传导的基本阻抗的数量，并根据测量结果估计驱动阻抗的阻抗值，并将电压除以校准阻抗和输出端的驱动阻抗。

    Hysterisis management for delay line
    9.
    发明授权
    Hysterisis management for delay line 有权
    滞后线管理

    公开(公告)号：US07205812B1

    公开(公告)日：2007-04-17

    申请号：US11147003

    申请日：2005-06-07

    申请人： Eer-Wen Tyan

    发明人： Eer-Wen Tyan

    IPC分类号： H03H11/26

    CPC分类号： H03K5/13 ,  H03K2005/00104

    摘要： A method and apparatus for managing hysterisis in a delay line. In one embodiment, an integrated circuit includes a delay line. A selection circuit is coupled to an input of the delay line. The selection circuit includes two inputs: a first input coupled to convey a signal such as a data signal or a data strobe signal, while the second input is coupled to convey a dummy clock signal. Control logic is coupled to monitor activity within the delay line. Upon detecting a lack of activity for a predetermined time period, the control logic is configured to cause the selection circuit to allow the dummy clock signal to be conveyed to the input of the delay line.

    摘要翻译： 一种用于在延迟线中管理滞后的方法和装置。 在一个实施例中，集成电路包括延迟线。 选择电路耦合到延迟线的输入端。 选择电路包括两个输入：耦合以传送诸如数据信号或数据选通信号的信号的第一输入，而第二输入被耦合以传送虚拟时钟信号。 控制逻辑耦合到监视延迟线内的活动。 当检测到预定时间段内的活动不足时，控制逻辑被配置为使得选择电路允许虚拟时钟信号被传送到延迟线的输入端。