公开(公告)号：US20140367689A1

公开(公告)日：2014-12-18

申请号：US14192239

申请日：2014-02-27

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Haeng CHO ,  Sang-Hee PARK ,  Chi-Sun HWANG

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/7869

Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.

Abstract translation: 提供一种晶体管。 晶体管包括：衬底; 半导体层，其设置在所述基板上，并且具有与所述基板垂直的一侧，所述另一侧面向所述一侧; 沿所述基板延伸并接触所述半导体层的一侧的第一电极; 第二电极，沿着衬底延伸并接触半导体层的另一侧; 布置在所述第一电极上并与所述第二电极间隔开的导线; 设置在所述半导体层上的栅电极; 以及设置在所述半导体层和所述栅电极之间的栅绝缘层，其中所述半导体层，所述第一电极和所述第二电极具有共面。

公开(公告)号：US20150318363A1

公开(公告)日：2015-11-05

申请号：US14800251

申请日：2015-07-15

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung Haeng CHO ,  Sang-Hee PARK ,  Chi-Sun HWANG

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/7869

Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.

Abstract translation: 提供一种晶体管。 晶体管包括：衬底; 半导体层，其设置在所述基板上，并且具有与所述基板垂直的一侧，所述另一侧面向所述一侧; 沿所述基板延伸并接触所述半导体层的一侧的第一电极; 第二电极，沿着衬底延伸并接触半导体层的另一侧; 布置在所述第一电极上并与所述第二电极间隔开的导线; 设置在所述半导体层上的栅电极; 以及设置在所述半导体层和所述栅电极之间的栅绝缘层，其中所述半导体层，所述第一电极和所述第二电极具有共面。

公开(公告)号：US20150171833A1

公开(公告)日：2015-06-18

申请号：US14335242

申请日：2014-07-18

Applicant: Konkuk University Industrial Cooperation Corp ,  Electronics and Telecommunications Research Institute

Inventor： Jae-Eun PI ,  Sang-Hee PARK ,  Min Ki RYU ,  Chi-Sun HWANG ,  OhSang KWON ,  Eunsuk PARK ,  Kee-Chan PARK ,  YeonKyung KIM

IPC: H03K3/012 ,  H03K5/01

CPC classification number: H03K3/012 ,  H03K4/026 ,  H03K5/01 ,  H03K5/05

Abstract: Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.

Abstract translation: 提供了一个栅极驱动电路。 栅极驱动器电路包括多个顺序连接的级，并且每个级包括一个输入单元，该输入单元包括形成二极管连接的两个输入晶体管，一个包括上拉晶体管和自举电容器的上拉单元，以及第一和第二上拉电路， 每个下降单元包括两个晶体管。 根据实施例，还包括输入电容器，其连接到输入单元和上拉单元之间的节点。 此外，还包括进位单元，其连接到输出端子并且被形成为将处于高状态或低状态的输出信号传输到下一级。

公开(公告)号：US20160240563A1

公开(公告)日：2016-08-18

申请号：US15043402

申请日：2016-02-12

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  Korea Advanced Institute of Science and Technology

Inventor： Sang-Hee PARK ,  Chi-Sun HWANG ,  Min Ki RYU ,  Jae-Eun PI ,  Jong-Beom KO ,  Hyein YEOM

IPC: H01L27/12 ,  H01L21/027 ,  H01L29/423 ,  H01L21/306 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/1225 ,  H01L21/0274 ,  H01L21/467 ,  H01L27/127 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided is a semiconductor device. The semiconductor device includes a second semiconductor pattern disposed on the substrate and configured to provide a channel region, and a first semiconductor pattern disposed between the substrate and the second semiconductor pattern, wherein the first semiconductor pattern includes a channel region that is a portion in contact with the second semiconductor pattern and source/drain regions that are portions exposed by the second semiconductor pattern.

Abstract translation: 提供一种半导体器件。 所述半导体器件包括设置在所述衬底上并被配置为提供沟道区的第二半导体图案，以及设置在所述衬底和所述第二半导体图案之间的第一半导体图案，其中所述第一半导体图案包括作为接触部分的沟道区 其中第二半导体图案和源极/漏极区域是由第二半导体图案暴露的部分。

公开(公告)号：US20140062572A1

公开(公告)日：2014-03-06

申请号：US14010579

申请日：2013-08-27

Applicant: Electronics and Telecommunications Research Institute ,  Konkuk University Industrial Cooperation Corp.

Inventor： Jae-Eun PI ,  Kee-Chan PARK ,  Sangyeon KIM ,  Joondong KIM ,  Yeon Kyung KIM ,  HongKyun LYM ,  Sang-Hee PARK ,  Byoung Gon YU ,  Chi-Sun HWANG ,  Jong Woo KIM ,  OhSang KWON ,  Min Ki RYU

IPC: H03K17/30

CPC classification number: H03K17/302 ,  H03K19/0185

Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.

Abstract translation: 提供单个输入电平移位器。 单输入电平移位器包括：输入单元，响应于输入信号向第一节点施加电源电压，并响应于参考信号将输入信号施加到第二节点; 引导单元，根据第一节点的电压电平向第二节点施加电源电压; 以及输出单元，其响应于所述参考信号将输入信号施加到输出端子，并且根据所述第一节点的电压电平将所述电源电压施加到所述输出端子，其中所述自举单元包括所述第一和第二节点之间的电容器 并且当所述输入信号从第一电压电平偏移到第二电压电平时，所述自举单元将所述第一节点的电压电平升高到高于所述电源电压的电平。