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公开(公告)号：US20140062572A1
公开(公告)日：2014-03-06
申请号：US14010579
申请日：2013-08-27
申请人： Electronics and Telecommunications Research Institute , Konkuk University Industrial Cooperation Corp.
发明人： Jae-Eun PI , Kee-Chan PARK , Sangyeon KIM , Joondong KIM , Yeon Kyung KIM , HongKyun LYM , Sang-Hee PARK , Byoung Gon YU , Chi-Sun HWANG , Jong Woo KIM , OhSang KWON , Min Ki RYU
IPC分类号： H03K17/30
CPC分类号： H03K17/302 , H03K19/0185
摘要： Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.
摘要翻译： 提供单个输入电平移位器。 单输入电平移位器包括：输入单元，响应于输入信号向第一节点施加电源电压，并响应于参考信号将输入信号施加到第二节点; 引导单元，根据第一节点的电压电平向第二节点施加电源电压; 以及输出单元，其响应于所述参考信号将输入信号施加到输出端子，并且根据所述第一节点的电压电平将所述电源电压施加到所述输出端子，其中所述自举单元包括所述第一和第二节点之间的电容器 并且当所述输入信号从第一电压电平偏移到第二电压电平时，所述自举单元将所述第一节点的电压电平升高到高于所述电源电压的电平。
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公开(公告)号：US20150171833A1
公开(公告)日：2015-06-18
申请号：US14335242
申请日：2014-07-18
申请人： Konkuk University Industrial Cooperation Corp , Electronics and Telecommunications Research Institute
发明人： Jae-Eun PI , Sang-Hee PARK , Min Ki RYU , Chi-Sun HWANG , OhSang KWON , Eunsuk PARK , Kee-Chan PARK , YeonKyung KIM
摘要： Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.
摘要翻译： 提供了一个栅极驱动电路。 栅极驱动器电路包括多个顺序连接的级，并且每个级包括一个输入单元，该输入单元包括形成二极管连接的两个输入晶体管，一个包括上拉晶体管和自举电容器的上拉单元，以及第一和第二上拉电路， 每个下降单元包括两个晶体管。 根据实施例，还包括输入电容器，其连接到输入单元和上拉单元之间的节点。 此外，还包括进位单元，其连接到输出端子并且被形成为将处于高状态或低状态的输出信号传输到下一级。
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公开(公告)号：US20230083225A1
公开(公告)日：2023-03-16
申请号：US17943528
申请日：2022-09-13
发明人： Jong-Heon YANG , Seung Youl KANG , Yong Hae KIM , Hee-ok KIM , Jeho NA , Jaehyun MOON , Chan Woo PARK , Himchan OH , Seong-Mok CHO , Sung Haeng CHO , Ji Hun CHOI , Jae-Eun PI , Chi-Sun HWANG
IPC分类号： H01L27/32 , G09G3/3266 , G09G3/3225
摘要： Provided are a semiconductor device, a display panel, and a display device including the same. The semiconductor device includes a lower electrode on one side of a substrate, a spacer on another side of the substrate, a middle electrode on the spacer, a lower channel layer on portions of a sidewall of the spacer, the middle electrode, and the lower electrode, a lower gate insulating layer on the lower channel layer, a common gate electrode on the gate insulating layer, an upper gate insulating layer on the common gate electrode, an upper electrode on the spacer and the upper gate insulating layer of the middle electrode, an upper channel layer connected to the upper electrode and disposed on a sidewall of the upper gate insulating layer, and a contact electrode connected to a portion of the upper channel layer and passing through the lower gate insulating layer and the upper gate insulating layer outside the common gate electrode so as to be connected to the lower electrode.
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公开(公告)号：US20160240563A1
公开(公告)日：2016-08-18
申请号：US15043402
申请日：2016-02-12
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE , Korea Advanced Institute of Science and Technology
发明人： Sang-Hee PARK , Chi-Sun HWANG , Min Ki RYU , Jae-Eun PI , Jong-Beom KO , Hyein YEOM
IPC分类号： H01L27/12 , H01L21/027 , H01L29/423 , H01L21/306 , H01L29/786 , H01L29/417
CPC分类号： H01L27/1225 , H01L21/0274 , H01L21/467 , H01L27/127 , H01L29/41733 , H01L29/42384 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： Provided is a semiconductor device. The semiconductor device includes a second semiconductor pattern disposed on the substrate and configured to provide a channel region, and a first semiconductor pattern disposed between the substrate and the second semiconductor pattern, wherein the first semiconductor pattern includes a channel region that is a portion in contact with the second semiconductor pattern and source/drain regions that are portions exposed by the second semiconductor pattern.
摘要翻译： 提供一种半导体器件。 所述半导体器件包括设置在所述衬底上并被配置为提供沟道区的第二半导体图案，以及设置在所述衬底和所述第二半导体图案之间的第一半导体图案，其中所述第一半导体图案包括作为接触部分的沟道区 其中第二半导体图案和源极/漏极区域是由第二半导体图案暴露的部分。
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公开(公告)号：US20240213372A1
公开(公告)日：2024-06-27
申请号：US18487625
申请日：2023-10-16
发明人： Yong Hae KIM , Jong-Heon YANG , Seong-Mok CHO , Ji Hun CHOI , Jae-Eun PI , Chi-Sun HWANG
IPC分类号： H01L29/786 , H01L27/06 , H01L29/417 , H01L29/66
CPC分类号： H01L29/78642 , H01L27/0629 , H01L28/20 , H01L29/41733 , H01L29/6675 , H01L29/66772 , H01L29/66969 , H01L29/78654 , H01L29/78672 , H01L29/7869 , H01L29/78696
摘要： Provided is a method for manufacturing a vertical channel thin film transistor. The method for manufacturing the vertical channel thin film transistor includes forming a bottom source drain electrode, forming a first interlayer insulating layer, forming first middle source drain electrodes, forming a second interlayer insulating layer, forming a top source drain electrode, forming an opening through which portions of the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode are exposed, forming channel layers, forming a gate insulating layer on the channel layers, the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode, and forming gate electrodes on the gate insulating layer.
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6.发明申请公开(公告)号：US20180026104A1
公开(公告)日：2018-01-25
申请号：US15621135
申请日：2017-06-13
发明人： Sung Haeng CHO , Sooji NAM , Chi-Sun HWANG , Su Jae LEE , Kyoung Ik CHO , Jae-Eun PI
IPC分类号： H01L29/24 , H01L21/02 , H01L29/786
CPC分类号： H01L29/24 , H01L21/02381 , H01L21/02565 , H01L21/02579 , H01L21/02617 , H01L21/0262 , H01L21/02623 , H01L21/02631 , H01L29/7869
摘要： Provided are a p-type oxide semiconductor, a method of forming the p-type oxide semiconductor, and a transistor with the p-type oxide semiconductor. The p-type oxide semiconductor includes an alkali metal and a tin oxide.
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公开(公告)号：US20160267827A1
公开(公告)日：2016-09-15
申请号：US15007856
申请日：2016-01-27
发明人： Chunwon BYUN , Jae-Eun PI , Kyoung Ik CHO , Hye Yong CHU , Chi-Sun HWANG
IPC分类号： G09G3/20
CPC分类号： G09G3/3648 , G09G3/3233 , G09G2300/023 , G09G2300/046 , G09G2300/0842
摘要： A display panel includes pixels connected to each of gate lines and data lines. Each of the pixels includes a first transistor connected between a corresponding data line among the data lines and a first node and configured to deliver a data signal of the corresponding data line to the first node in response to an input signal received through a corresponding gate line among the gate lines, a reflective element circuit connected to the first node, and configured to implement the reflective mode in response to a signal of the first node when a first mode selection signal indicates a reflective mode, an emissive element circuit connected to a second node, and configured to implement the emissive mode in response to the signal of the first node when the mode selection mode indicates an emissive mode.
摘要翻译： 显示面板包括连接到每条栅极线和数据线的像素。 每个像素包括连接在数据线中的对应数据线和第一节点之间的第一晶体管，并且被配置为响应于通过对应的栅极线接收的输入信号将对应的数据线的数据信号传送到第一节点 在所述栅极线之间，连接到所述第一节点的反射元件电路，并且被配置为当第一模式选择信号指示反射模式时，响应于所述第一节点的信号来实现所述反射模式;连接到第二节点的发射元件电路 并且被配置为当模式选择模式指示发射模式时响应于第一节点的信号来实现发射模式。
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8.发明申请OXIDE TRANSISTOR WITH NANO-LAYERED STRUCTURE AND METHOD OF FABRICATING THE SAME 有权具有纳米结构的氧化物晶体及其制造方法公开(公告)号：US20140159036A1
公开(公告)日：2014-06-12
申请号：US14020498
申请日：2013-09-06
发明人： Su Jae LEE , Chi-Sun HWANG , Hye Yong CHU , Sang Chul LIM , Jae-Eun PI , Min Ki RYU
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L29/66969 , H01L29/78696
摘要： According to example embodiments of the inventive concept, provided is a transistor with a nano-layered oxide semiconductor layer. The oxide semiconductor layer may include at least one first nano layer and at least one second nano layer that are alternatingly stacked one on another. Here, the first nano layer and the second nano layer may include different materials from each other, and thus, a channel with high electron mobility may be formed at the interface between the first and second nano layers. Accordingly, the transistor can have high reliability.
摘要翻译： 根据本发明构思的示例性实施例，提供了具有纳米层氧化物半导体层的晶体管。 氧化物半导体层可以包括交替堆叠在一起的至少一个第一纳米层和至少一个第二纳米层。 这里，第一纳米层和第二纳米层可以包括彼此不同的材料，因此，可以在第一和第二纳米层之间的界面处形成具有高电子迁移率的沟道。 因此，晶体管可以具有高的可靠性。
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公开(公告)号：US20230097393A1
公开(公告)日：2023-03-30
申请号：US17520853
申请日：2021-11-08
发明人： Sung Haeng CHO , Byung-Do YANG , Sooji NAM , Jaehyun MOON , Jae-Eun PI , Jae-Min KIM
IPC分类号： H01L27/092 , H01L29/24 , H03K19/0185 , H03K19/0948 , H01L27/02
摘要： Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.
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公开(公告)号：US20220199836A1
公开(公告)日：2022-06-23
申请号：US17523320
申请日：2021-11-10
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE , Korea Advanced Institute of Science and Technology
发明人： Chi-Sun HWANG , SangHee PARK , KwangHeum LEE , Jae-Eun PI , SeungHee LEE , Jong-Heon YANG , Ji Hun CHOI
IPC分类号： H01L29/786 , H01L29/66 , H01L29/40 , H01L29/49
摘要： A vertical channel thin film transistor includes substrate, lower source/drain electrode, spacer layer, upper source/drain electrode covering portion of upper surface of the spacer layer, interlayer insulating pattern covering portion of upper surface of the upper source/drain electrode and upper surface of the spacer layer exposed by the upper source/drain electrode, contact hole disposed on the lower source/drain electrode and passing through the interlayer insulating pattern, the upper source/drain electrode, and the spacer layer, active pattern covering inner wall and bottom surface of the contact hole and extending over upper surface of the upper source/drain electrode and upper surface of the interlayer insulating pattern, gate insulating pattern filling portion of the contact hole and extending along upper surface of the active pattern, and gate electrode filling portion of the contact hole and extending along upper surface of the gate insulating pattern.
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