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1.发明申请公开(公告)号：US20250158604A1
公开(公告)日：2025-05-15
申请号：US18940129
申请日：2024-11-07
Inventor： Yi-Gyeong KIM , Young-Su KWON , Su-Jin PARK , Young-Deuk JEON , Min-Hyung CHO
Abstract: Disclosed herein is a high-speed I/O circuit for die-to-die interconnect for suppressing an overshoot and an undershoot. A data reception circuit includes a reception circuit configured to convert a reception signal received from an interconnect into a digital signal, a first clipper circuit configured to suppress an overshoot of the reception signal based on current extraction, and a second clipper circuit configured to suppress an undershoot of the reception signal based on current supply.
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公开(公告)号：US20250067841A1
公开(公告)日：2025-02-27
申请号：US18733086
申请日：2024-06-04
Inventor： Yi-Gyeong KIM , Kyung Hwan Park , Sujin Park , Young-deuk Jeon , Min-Hyung Cho
Abstract: Disclosed is an ultra-wide band (UWB) radar device including a first antenna circuit including a first transmission circuit, a first reception circuit, a first oscillator that supplies a first clock signal to the first transmission circuit and the first reception circuit, and a first frequency counter, a second antenna circuit including a second transmission circuit, a second reception circuit, a second oscillator that supplies a second clock signal to the second transmission circuit and the second reception circuit, and a second frequency counter, and a controller that detects the target. The controller corrects a frequency error between the first clock signal and the second clock signal and compensates for a synchronization error between the first antenna circuit and the second antenna circuit.
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公开(公告)号：US20240195399A1
公开(公告)日：2024-06-13
申请号：US18223101
申请日：2023-07-18
Inventor： Yi-Gyeong KIM , Young-Su KWON , Su-Jin PARK , Young-Deuk JEON , Min-Hyung CHO , Jae-Woong CHOI
CPC classification number: H03K5/1565 , G06F1/12 , G11C11/4076 , H03K5/131 , H03K5/135 , H03L7/0812 , H03K2005/00058
Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
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4.发明申请公开(公告)号：US20180146155A1
公开(公告)日：2018-05-24
申请号：US15653358
申请日：2017-07-18
Inventor： Chun-Gi LYUH , Yi-Gyeong KIM , Jung Hee SUK , Young-Deuk JEON , Min-Hyung CHO
CPC classification number: H04N5/4448 , H04N5/05 , H04N5/23238 , H04N19/44
Abstract: The present disclosure relates to a frame grabber, an image processing system, and an image processing method. A frame grabber according to an embodiment of the inventive concept includes a plurality of decoders, a plurality of image controllers, a plurality of memories, a synchronization controller, and a synchronization memory. The plurality of decoders generate a plurality of image data by decoding a plurality of image signals. The plurality of image controllers generate a plurality of pixel data and a plurality of frame information data on the basis of the plurality of image data. The plurality of memories store the plurality of pixel data. The synchronization controller receives the plurality of frame information data, and generates synchronization data on the basis of the plurality of frame information data. The synchronization memory stores the frame information data and the synchronization data.
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5.发明申请公开(公告)号：US20140132326A1
公开(公告)日：2014-05-15
申请号：US13922647
申请日：2013-06-20
Inventor： Yi-Gyeong KIM , Tae Moon ROH , Jong-Kee KWON
IPC: H03K5/08
CPC classification number: H03K5/088
Abstract: Provided is a pulse noise suppression circuit. The pulse noise suppression circuit includes a filter circuit converting an input signal of a pulse type into an increasing or decreasing filter signal, a level reset circuit resetting the filter signal in response to the input signal and an output signal and an output circuit converting the filter signal into the output signal of a pulse type, wherein the level reset circuit resets the filter signal to have a high level when the input signal and the output signal all have a high level, and resets the filter signal to have a low level when the input signal and the output signal all have a low level.
Abstract translation: 提供了一种脉冲噪声抑制电路。 脉冲噪声抑制电路包括将脉冲类型的输入信号转换成增减滤波器信号的滤波器电路，响应于输入信号和输出信号复位滤波器信号的电平复位电路以及转换滤波器的输出电路 信号输入到脉冲类型的输出信号中，其中当输入信号和输出信号都具有高电平时，电平复位电路使滤波器信号复位为具有高电平，并且当滤波器信号为低电平时，复位滤波器信号以具有低电平 输入信号和输出信号都具有低电平。
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Patent Agency Ranking
公开(公告)号：US20240194241A1
公开(公告)日：2024-06-13
申请号：US18223097
申请日：2023-07-18
Inventor： Young-Deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO , Jae-Woong CHOI
IPC: G11C11/4074 , G11C11/4076
CPC classification number: G11C11/4074 , G11C11/4076
Abstract: Disclosed herein is an apparatus for adjusting a reference voltage. The apparatus may include a gate signal generation unit for generating an RDQS gate signal, a reference voltage generation unit for setting a reference voltage based on the RDQS gate signal, and a reset counter for holding a voltage at the time at which the RDQS gate signal becomes low when the RDQS gate signal is not applied to the reference voltage generation unit for a specific time period.
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公开(公告)号：US20180138882A1
公开(公告)日：2018-05-17
申请号：US15684625
申请日：2017-08-23
Inventor： Yi-Gyeong KIM , Woo Seok YANG , Min-Hyung CHO
IPC: H03G3/30
CPC classification number: H03G3/3089 , H03G3/3005 , H03G3/3026 , H04R1/08 , H04R3/00 , H04R2410/03
Abstract: The present disclosure relates to a microphone driving device and a digital microphone including the same. A microphone driving device according to an embodiment of the inventive concept includes a voltage-to-current converter, a current-to-voltage converter, an analog-to-digital converter, a digital amplification unit, and a gain controller. The voltage-to-current converter converts an acoustic signal to an output current signal based on a gain control signal. The current-to-voltage converter converts the output current signal to an amplified voltage signal. The analog-to-digital converter converts the amplified voltage signal to a digital signal. The digital amplification unit amplifies the digital signal to an amplified digital signal based on the gain control signal. The gain controller generates a gain control signal. The microphone driving device and the digital microphone including the same according to the inventive concept may have a wide dynamic range and reduce the influence of noise.
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8.发明申请ANALOG-TO-DIGITAL CONVERTING DEVICE AND METHOD OF OPERATING ANALOG-TO-DIGITAL CONVERTING DEVICE 有权模拟数字转换器件和操作模拟数字转换器件的方法公开(公告)号：US20160336951A1
公开(公告)日：2016-11-17
申请号：US15083096
申请日：2016-03-28
Inventor： Young-deuk JEON , MIN-HYUNG CHO , Yi-Gyeong KIM , Chun-Gi LYUH
Abstract: Provided is an analog-to-digital converting device. The analog-to-digital converting device may include a determination circuit that determination whether a reference digital signal or a determination digital signal obtained by conversion of a reference voltage or a determination voltage matches a test pattern for the reference voltage, and it is possible to monitor whether the analog-to-digital converting device normally operates, according to whether there is matching.
Abstract translation: 提供了一种模拟 - 数字转换装置。 模拟数字转换装置可以包括确定电路，其确定参考数字信号或通过转换参考电压或确定电压获得的确定数字信号是否与参考电压的测试模式匹配，并且可以 根据是否存在匹配，监控模数转换设备是否正常运行。
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公开(公告)号：US20250157499A1
公开(公告)日：2025-05-15
申请号：US18820449
申请日：2024-08-30
Inventor： Young-Deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO
Abstract: Disclosed herein is a reference voltage calibration apparatus in a memory interface. The reference voltage calibration apparatus includes a first low-pass filter configured to receive a clock signal, a second low-pass filter configured to receive an inverted clock signal that is an inverted signal of the clock signal, a first comparator configured to compare an output of the first low-pass filter with a reference voltage, a second comparator configured to compare an output of the second low-pass filter with the reference voltage, an up/down counter configured to count upward or downward from output values of the first comparator and the second comparator, respectively, and a digital-to-analog converter configured to convert an up/down counter value into an analog signal, and then output the reference voltage, wherein the digital-to-analog converter applies a calibration voltage based on the reference voltage to the first low-pass filter and to the second low-pass filter.
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公开(公告)号：US20250052860A1
公开(公告)日：2025-02-13
申请号：US18788357
申请日：2024-07-30
Inventor： Young-deuk JEON , Yi-Gyeong KIM , Kyung Hwan PARK , Sujin PARK , MIN-HYUNG CHO
Abstract: Disclosed is a receiver of a radar device, which includes a sampling circuit that receives a reflected pulse signal having a first period reflected from a detection target and samples the reflected pulse signal as a first received signal in response to a clock signal having a second period equal to the first period, an integration circuit that, in response to the clock signal, generates an analog integration signal based on the first received signal and a control signal, a comparison circuit that, in response to the clock signal, adjusts a count value and the control signal based on a result of comparing the analog integration signal with a reference signal and outputs the control signal to the integration circuit, and an ADC circuit that converts the analog integration signal into a digital integration signal.
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