公开(公告)号：US6051443A

公开(公告)日：2000-04-18

申请号：US990617

申请日：1997-12-15

申请人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese ,  Fran.cedilla.ois Maugain ,  Giovanni Rivera

发明人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese ,  Fran.cedilla.ois Maugain ,  Giovanni Rivera

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L22/12

摘要： A method for assessing alterations in the dielectric properties of insulating layers on a wafer of semiconductor material induced by plasma treatments. The method includes forming cells of EEPROM type on a wafer with source, drain and control gate surface terminals (pads), subjecting the cells to UV radiation so as to erase them thereby fixing a reference threshold voltage, applying programming voltages of preset value to at least one of the cells and measuring the corresponding threshold voltages, and subjecting this cell to UV radiation so as to restore its threshold to the reference value. The wafer is then subjected to the plasma treatment to be assessed, and the threshold voltages of the cells are measured and compared with the reference threshold voltage so as to derive from the comparison information on the alterations induced on the dielectrics formed on the wafer and on the distribution of the plasma potential.

摘要翻译： 用于评估由等离子体处理引起的半导体材料的晶片上的绝缘层的介电性质的变化的方法。 该方法包括在晶片上形成具有源极，漏极和控制栅极表面端子（焊盘）的EEPROM型电池，使电池经受紫外辐射，从而擦除它们，从而固定参考阈值电压，将预设值的编程电压施加到 至少一个电池并测量相应的阈值电压，并对该电池进行紫外辐射，以将其阈值恢复到参考值。 然后对晶片进行等离子体处理以进行评估，并测量电池的阈值电压并将其与参考阈值电压进行比较，以便从关于在晶片上形成的电介质上引起的变化的比较信息导出 等离子体电位的分布。

公开(公告)号：US5888836A

公开(公告)日：1999-03-30

申请号：US990328

申请日：1997-12-15

申请人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese

发明人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/268

CPC分类号： H01L29/66825 ,  H01L21/28176

摘要： The process described requires the formation of floating-gate non-volatile memory cells entirely similar in structure to those produced by known processes. The process comprises an annealing treatment at relatively low temperature (430.degree. C.) to repair damage due to plasma treatments. To obtain threshold voltage values for the cells close to the theoretical values, especially for cells with particularly extended interconnections, the cells are subjected to ultraviolet radiation before the annealing treatment, in order to neutralize any electrical charges present in the floating-gate electrodes of the cells.

摘要翻译： 所描述的方法需要形成与已知方法制造的那些结构完全相似的浮栅非易失性存储单元。 该方法包括在较低温度（430℃）下进行退火处理，以修复等离子体处理造成的损坏。 为了获得接近理论值的电池的阈值电压值，特别是对于具有特别延长的互连的电池，在退火处理之前对电池进行紫外线辐射，以便中和存在于浮栅电极中的任何电荷 细胞。

公开(公告)号：US6087228A

公开(公告)日：2000-07-11

申请号：US890052

申请日：1997-07-09

申请人： Emilio Ghio ,  Giuseppe Meroni

发明人： Emilio Ghio ,  Giuseppe Meroni

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/8236

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： The invention relates to a method of automatically shifting from the fabrication of an EPROM cell to the fabrication of a ROM cell, which method is specifically intended for semiconductor electronic circuits having a resident memory and is of the type wherein the structure of at least one memory cell transistor is defined on a semiconductor substrate using photolithographic techniques including an active area and a channel region, the cell being adapted to acquire a logic state selected by the user. Advantageously, the conductivity of the active area is changed to suit the logical contents that the cell is intended to contain.

摘要翻译： 本发明涉及一种自动从EPROM单元的制造转移到ROM单元的制造方法，该方法专门用于具有驻留存储器的半导体电子电路，并且是其中至少一个存储器的结构 使用包括有源区域和沟道区域的光刻技术在半导体衬底上限定单元晶体管，该单元适于获取由用户选择的逻辑状态。 有利地，有源区域的电导率被改变以适应单元意图包含的逻辑内容。

公开(公告)号：US5793085A

公开(公告)日：1998-08-11

申请号：US481928

申请日：1995-06-07

申请人： Bruno Vajana ,  Emilio Ghio

发明人： Bruno Vajana ,  Emilio Ghio

IPC分类号： H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/76

CPC分类号： H01L21/8249 ,  H01L21/8248 ,  H01L27/0623

摘要： A bipolar transistor, comprising a collector region, a base region, and an emitter region, is a type which is compatible to CMOS processes leading to the formation, on a semiconductor substrate, of N-channel and P-channel MOS transistors having respective source and drain regions. In such bipolar transistor, the collector region is a substrate diffused pocket and the base region is formed within the diffused pocket simultaneously with the source and drain regions of the P-channel MOS transistors. Further, the emitter region is incorporated, in turn, to the base region simultaneously with the source and drain regions of the N-channel MOS transistors.

摘要翻译： 包括集电极区域，基极区域和发射极区域的双极晶体管是与CMOS工艺兼容的类型，其导致在半导体衬底上形成具有相应源极的N沟道和P沟道MOS晶体管 和漏区。 在这种双极性晶体管中，集电极区域是衬底扩散的阱，并且基底区域与P沟道MOS晶体管的源极和漏极区域同时形成在扩散的凹穴内。 此外，发射极区域又与N沟道MOS晶体管的源极和漏极区域同时并入基极区域。