公开(公告)号：US6051443A

公开(公告)日：2000-04-18

申请号：US990617

申请日：1997-12-15

申请人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese ,  Fran.cedilla.ois Maugain ,  Giovanni Rivera

发明人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese ,  Fran.cedilla.ois Maugain ,  Giovanni Rivera

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L22/12

摘要： A method for assessing alterations in the dielectric properties of insulating layers on a wafer of semiconductor material induced by plasma treatments. The method includes forming cells of EEPROM type on a wafer with source, drain and control gate surface terminals (pads), subjecting the cells to UV radiation so as to erase them thereby fixing a reference threshold voltage, applying programming voltages of preset value to at least one of the cells and measuring the corresponding threshold voltages, and subjecting this cell to UV radiation so as to restore its threshold to the reference value. The wafer is then subjected to the plasma treatment to be assessed, and the threshold voltages of the cells are measured and compared with the reference threshold voltage so as to derive from the comparison information on the alterations induced on the dielectrics formed on the wafer and on the distribution of the plasma potential.

摘要翻译： 用于评估由等离子体处理引起的半导体材料的晶片上的绝缘层的介电性质的变化的方法。 该方法包括在晶片上形成具有源极，漏极和控制栅极表面端子（焊盘）的EEPROM型电池，使电池经受紫外辐射，从而擦除它们，从而固定参考阈值电压，将预设值的编程电压施加到 至少一个电池并测量相应的阈值电压，并对该电池进行紫外辐射，以将其阈值恢复到参考值。 然后对晶片进行等离子体处理以进行评估，并测量电池的阈值电压并将其与参考阈值电压进行比较，以便从关于在晶片上形成的电介质上引起的变化的比较信息导出 等离子体电位的分布。

公开(公告)号：US5888836A

公开(公告)日：1999-03-30

申请号：US990328

申请日：1997-12-15

申请人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese

发明人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/268

CPC分类号： H01L29/66825 ,  H01L21/28176

摘要： The process described requires the formation of floating-gate non-volatile memory cells entirely similar in structure to those produced by known processes. The process comprises an annealing treatment at relatively low temperature (430.degree. C.) to repair damage due to plasma treatments. To obtain threshold voltage values for the cells close to the theoretical values, especially for cells with particularly extended interconnections, the cells are subjected to ultraviolet radiation before the annealing treatment, in order to neutralize any electrical charges present in the floating-gate electrodes of the cells.

摘要翻译： 所描述的方法需要形成与已知方法制造的那些结构完全相似的浮栅非易失性存储单元。 该方法包括在较低温度（430℃）下进行退火处理，以修复等离子体处理造成的损坏。 为了获得接近理论值的电池的阈值电压值，特别是对于具有特别延长的互连的电池，在退火处理之前对电池进行紫外线辐射，以便中和存在于浮栅电极中的任何电荷 细胞。

公开(公告)号：US07569492B1

公开(公告)日：2009-08-04

申请号：US12111095

申请日：2008-04-28

申请人： David L. Chen ,  Yuh-Jia Su ,  Eddie Ka Ho Chiu ,  Maria Paola Pozzoli ,  Senzi Li ,  Giuseppe Colangelo ,  Simone Alba ,  Simona Petroni

发明人： David L. Chen ,  Yuh-Jia Su ,  Eddie Ka Ho Chiu ,  Maria Paola Pozzoli ,  Senzi Li ,  Giuseppe Colangelo ,  Simone Alba ,  Simona Petroni

IPC分类号： H01L21/302

CPC分类号： B08B7/0035 ,  H01J2237/335 ,  H01L21/02063 ,  H01L21/02071

摘要： The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used. Embodiments of the invention are performed after an etch, such as a metal etch, via etch, contact etch, polysilicon etch, nitride etch or shallow trench isolation etch has been performed. Photoresist may be removed either prior to, during, or after cleaning processes according to embodiments of the invention, using an oxygen-containing plasma. Photoresist removal may be performed at low temperatures.

摘要翻译： 本发明提供了用于执行清洁过程的方法，其提供更高的清洁效率，同时对设备结构的损坏较小。 在蚀刻和光致抗蚀剂剥离之后，进行第一等离子体清洁。 第一等离子体清洁可以包括一个或多个步骤。 在第一次等离子体清洁之后，执行第一次基于HO的清洁。 第一个基于HO的清洁可以是去离子水冲洗，水蒸气清洁或等离子体清洁，其中等离子体包括氢和氧。 在第一个基于HO的清洁之后，执行第二等离子体清洁，其可以包括一个或多个步骤。 第二个基于HO的清洁遵循第二等离子体清洁，并且可以是去离子水冲洗，水蒸汽清洁或等离子体清洁，其中等离子体包括氢和氧。 对于等离子体处理，可以使用RF产生的等离子体，微波产生的等离子体，电感耦合等离子体或组合。 通过蚀刻，接触蚀刻，多晶硅蚀刻，氮化物蚀刻或浅沟槽隔离蚀刻等蚀刻，例如金属蚀刻，进行本发明的实施例。 可以使用含氧等离子体在根据本发明的实施方案的清洁方法之前，期间或之后除去光致抗蚀剂。 可以在低温下进行光刻胶去除。

公开(公告)号：US20050239291A1

公开(公告)日：2005-10-27

申请号：US11089942

申请日：2005-03-25

申请人： Simone Alba ,  Carmelo Romeo

发明人： Simone Alba ,  Carmelo Romeo

IPC分类号： G03F1/20 ,  G03F7/00 ,  H01L21/302

CPC分类号： G03F7/0015 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788

摘要： A method for defining geometries in a semiconductor wafer supported on a plate electrode in a processing chamber includes forming a reusable refractory coated laminar mask. The reusable refractory coated laminar mask is formed by defining the geometries in a laminar mask substrate, forming apertures through the laminar mask substrate, and forming a layer of refractory material over at least one surface of the laminar mask substrate. The reusable refractory coated laminar mask is positioned over the semiconductor wafer. Treating of the semiconductor wafer is performed through the apertures of the reusable refractory coated laminar mask. The treating may be plasma etching or ion etching.

摘要翻译： 在处理室中支撑在板电极上的半导体晶片中限定几何形状的方法包括形成可重复使用的耐火涂层层状掩模。 通过限定层状掩模基板中的几何形状，通过层状掩模基板形成孔，并在层状掩模基板的至少一个表面上形成耐火材料层，形成可重复使用的难熔涂层的层状掩模。 可重复使用的耐火涂层层状掩模位于半导体晶片上。 半导体晶片的处理通过可重复使用的耐火涂层的层状掩模的孔进行。 该处理可以是等离子体蚀刻或离子蚀刻。

公开(公告)号：US07288008B2

公开(公告)日：2007-10-30

申请号：US11089942

申请日：2005-03-25

申请人： Simone Alba ,  Carmelo Romeo

发明人： Simone Alba ,  Carmelo Romeo

IPC分类号： H01L21/302

CPC分类号： G03F7/0015 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788

摘要： A method for defining geometries in a semiconductor wafer supported on a plate electrode in a processing chamber includes forming a reusable refractory coated laminar mask. The reusable refractory coated laminar mask is formed by defining the geometries in a laminar mask substrate, forming apertures through the laminar mask substrate, and forming a layer of refractory material over at least one surface of the laminar mask substrate. The reusable refractory coated laminar mask is positioned over the semiconductor wafer. Treating of the semiconductor wafer is performed through the apertures of the reusable refractory coated laminar mask. The treating may be plasma etching or ion etching.

摘要翻译： 在处理室中支撑在板电极上的半导体晶片中限定几何形状的方法包括形成可重复使用的耐火涂层层状掩模。 通过限定层状掩模基板中的几何形状，通过层状掩模基板形成孔，并在层状掩模基板的至少一个表面上形成耐火材料层，形成可重复使用的难熔涂层的层状掩模。 可重复使用的耐火涂层层状掩模位于半导体晶片上。 半导体晶片的处理通过可重复使用的耐火涂层的层状掩模的孔进行。 该处理可以是等离子体蚀刻或离子蚀刻。

公开(公告)号：US20080001295A1

公开(公告)日：2008-01-03

申请号：US11855229

申请日：2007-09-14

申请人： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

发明人： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

IPC分类号： H01L23/48

CPC分类号： H01L21/76838 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/76834

摘要： The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

摘要翻译： 该方法防止半导体器件中的导电互连结构的氧化或污染现象，并且包括在基底层上提供半导体层或氧化物层，导电层或叠层，以及导电层或叠层上的抗反射涂层（ARC）层。 该方法在抗反射涂层上提供薄的电介质覆盖层，以填充或覆盖存在于抗反射涂层中的微裂缝。

公开(公告)号：US20060105574A1

公开(公告)日：2006-05-18

申请号：US11280186

申请日：2005-11-16

申请人： Samantha Regini ,  Simone Alba

发明人： Samantha Regini ,  Simone Alba

IPC分类号： H01L21/461 ,  C23F1/00 ,  H01L21/302

CPC分类号： H01L21/0273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139

摘要： A process for the definition of integrated circuits on a wafer having at least one silicon semiconductor layer includes masking the wafer with a photoresist layer. The process includes a development step of the photoresist with definition of a lithographic pattern, a hardening step of the photoresist with a plasma of inert gas, and a dry etching step with a plasma of reactive gas for transferring the lithographic pattern on the wafer. The dry etching step includes at least an initial step, or breakthrough, with a plasma of a chlorinated gas and of an inert gas for removal of a silicon native oxide grown on the wafer.

摘要翻译： 用于在具有至少一个硅半导体层的晶片上定义集成电路的方法包括用光致抗蚀剂层掩蔽晶片。 该方法包括具有光刻图案定义的光致抗蚀剂的显影步骤，具有惰性气体等离子体的光致抗蚀剂的硬化步骤以及用于将平版印刷图案转印到晶片上的反应气体等离子体的干蚀刻步骤。 干蚀刻步骤至少包括用氯化气体的等离子体和用于去除在晶片上生长的硅自然氧化物的惰性气体的初始步骤或穿透。

公开(公告)号：US06998348B2

公开(公告)日：2006-02-14

申请号：US10428338

申请日：2003-05-01

申请人： Francesco Ciovacco ,  Simone Alba ,  Roberto Colombo ,  Chiara Savardi

发明人： Francesco Ciovacco ,  Simone Alba ,  Roberto Colombo ,  Chiara Savardi

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/823437 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816

摘要： A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.

公开(公告)号：US06233046B1

公开(公告)日：2001-05-15

申请号：US09343207

申请日：1999-06-29

申请人： Simone Alba ,  Claudio Savoia ,  Enrico Bellandi ,  Francesca Canali

发明人： Simone Alba ,  Claudio Savoia ,  Enrico Bellandi ,  Francesca Canali

IPC分类号： G01B1106

CPC分类号： G01B11/0641 ,  G01N21/211

摘要： The method described comprises the following steps: measuring, with a spectroscopic ellipsometer, the values of two quantities which are dependent on the thickness of the altered silicon layer and of a thin layer of silicon dioxide grown thereon with variations in the wavelength of the light of the measurement beam of the ellipsometer, obtaining from these measured values respective experimental curves representing the two quantities as functions of the wavelength, calculating the theoretical curves of the two quantities as functions of the wavelength considering the refractive indices and absorption coefficients of silicon dioxide and of the altered silicon as known parameters and the thickness of the altered silicon layer and the thickness of the thin silicon dioxide layer as unknowns, comparing the theoretical curves with the respective experimental curves in order to determine for which values of the unknowns the curves under comparison approximate to one another best, and extracting from the values determined the value which relates to the thickness of the altered silicon layer. The time required for the measurements and calculations is a few minutes.

摘要翻译： 所描述的方法包括以下步骤：用分光椭偏仪测量取决于改变的硅层的厚度和生长在其上的二氧化硅薄层的两个量的值，其中光的波长有变化 椭圆计的测量光束，从这些测量值获得表示两个量作为波长函数的各实验曲线，考虑二氧化硅的折射率和吸收系数计算两个量的函数的理论曲线，以及 改变的硅作为已知参数，并且改变的硅层的厚度和薄二氧化硅层的厚度为未知数，将理论曲线与各实验曲线进行比较，以确定未知量的哪些值比较曲线近似 彼此最好，并且提取 g的值取决于与改变的硅层的厚度有关的值。测量和计算所需的时间是几分钟。

公开(公告)号：US08058181B1

公开(公告)日：2011-11-15

申请号：US12502130

申请日：2009-07-13

申请人： David L. Chen ,  Yuh-Jia Su ,  Eddie Ka Ho Chiu ,  Maria Paola Pozzoli ,  Senzi Li ,  Giuseppe Colangelo ,  Simone Alba ,  Simona Petroni

发明人： David L. Chen ,  Yuh-Jia Su ,  Eddie Ka Ho Chiu ,  Maria Paola Pozzoli ,  Senzi Li ,  Giuseppe Colangelo ,  Simone Alba ,  Simona Petroni

IPC分类号： H01L21/302

CPC分类号： B08B7/0035 ,  H01J2237/335 ,  H01L21/02063 ,  H01L21/02071

摘要： The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF, generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used. Embodiments of the invention are performed after an etch, such as a metal etch, via etch, contact etch, polysilicon etch, nitride etch or shallow trench isolation etch has been performed. Photoresist may be removed either prior to, during, or after cleaning processes according to embodiments of the invention, using an oxygen-containing plasma. Photoresist removal may be performed at low temperatures.

摘要翻译： 本发明提供了用于执行清洁过程的方法，其提供更高的清洁效率，同时对设备结构的损坏较小。 在蚀刻和光致抗蚀剂剥离之后，进行第一等离子体清洁。 第一等离子体清洁可以包括一个或多个步骤。 在第一次等离子体清洁之后，执行第一次基于HO的清洁。 第一个基于HO的清洁可以是去离子水冲洗，水蒸气清洁或等离子体清洁，其中等离子体包括氢和氧。 在第一个基于HO的清洁之后，执行第二等离子体清洁，其可以包括一个或多个步骤。 第二个基于HO的清洁遵循第二等离子体清洁，并且可以是去离子水冲洗，水蒸汽清洁或等离子体清洁，其中等离子体包括氢和氧。 对于等离子体处理，可以使用RF，产生的等离子体，微波产生的等离子体，电感耦合等离子体或组合。 通过蚀刻，接触蚀刻，多晶硅蚀刻，氮化物蚀刻或浅沟槽隔离蚀刻等蚀刻，例如金属蚀刻，进行本发明的实施例。 可以使用含氧等离子体在根据本发明的实施方案的清洁方法之前，期间或之后除去光致抗蚀剂。 可以在低温下进行光刻胶去除。