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    Method of manufacturing dummy gates of a different material as insulation between adjacent devices
    5.
    发明授权
    Method of manufacturing dummy gates of a different material as insulation between adjacent devices 有权
    制造不同材料的虚拟栅极作为相邻器件之间绝缘的方法

    公开(公告)号：US09059308B2

    公开(公告)日：2015-06-16

    申请号：US13564792

    申请日：2012-08-02

    申请人： Emre Alptekin ,  Gregory Allen Northrop ,  Viraj Yashawant Sardesai ,  Cung Do Tran

    发明人： Emre Alptekin ,  Gregory Allen Northrop ,  Viraj Yashawant Sardesai ,  Cung Do Tran

    IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/49

    CPC分类号： H01L21/823481 ,  H01L21/823437 ,  H01L21/823828 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66545

    摘要： Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.

    摘要翻译： 本发明的实施例包括由不同材料的虚拟栅极隔开的两个晶体管结构的半导体结构和用于形成所述结构的方法。 实施例包括在半导体衬底上形成牺牲栅极，在牺牲栅上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源/漏区，以及用绝缘材料代替第三牺牲栅。 替代第三牺牲栅极的绝缘材料可以用作虚拟栅极以电隔离附近的源极/漏极区域。 实施例还包括在半导体衬底上形成牺牲栅极，在牺牲栅极上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源极/漏极区域，并且在离开第三牺牲栅极的同时用金属栅极替换两个牺牲栅极 到位作为虚拟门。

    Method of Manufacturing Dummy Gates of a Different Material as Insulation between Adjacent Devices
    6.
    发明申请
    Method of Manufacturing Dummy Gates of a Different Material as Insulation between Adjacent Devices 有权
    制造不同材料的虚拟门的方法作为相邻设备之间的绝缘

    公开(公告)号：US20140035045A1

    公开(公告)日：2014-02-06

    申请号：US13564792

    申请日：2012-08-02

    申请人： Emre Alptekin ,  Gregory Allen Northrop ,  Viraj Yashawant Sardesai ,  Cung Do Tran

    发明人： Emre Alptekin ,  Gregory Allen Northrop ,  Viraj Yashawant Sardesai ,  Cung Do Tran

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L21/823481 ,  H01L21/823437 ,  H01L21/823828 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66545

    摘要： Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.

    摘要翻译： 本发明的实施例包括由不同材料的虚拟栅极隔开的两个晶体管结构的半导体结构和用于形成所述结构的方法。 实施例包括在半导体衬底上形成牺牲栅极，在牺牲栅上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源/漏区，以及用绝缘材料代替第三牺牲栅。 替代第三牺牲栅极的绝缘材料可以用作虚拟栅极以电隔离附近的源极/漏极区域。 实施例还包括在半导体衬底上形成牺牲栅极，在牺牲栅极上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源极/漏极区域，并且在离开第三牺牲栅极的同时用金属栅极替换两个牺牲栅极 到位作为虚拟门。

    Structure and method of creating entirely self-aligned metallic contacts
    7.
    发明授权
    Structure and method of creating entirely self-aligned metallic contacts 有权
    创建完全自对准的金属触点的结构和方法

    公开(公告)号：US08298934B2

    公开(公告)日：2012-10-30

    申请号：US13155056

    申请日：2011-06-07

    申请人： Jeffery B. Maxson ,  Cung Do Tran ,  Huilong Zhu

    发明人： Jeffery B. Maxson ,  Cung Do Tran ,  Huilong Zhu

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/7833 ,  H01L21/28052 ,  H01L21/288 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.

    摘要翻译： 提供具有完全自对准金属接触的半导体结构。 半导体结构包括位于半导体衬底的表面上的至少一个场效应晶体管。 所述至少一个场效应晶体管包括包括多晶硅的下层和第一金属半导体合金的上层的栅极导体堆叠，所述栅极导体堆叠具有包括至少一个间隔物的侧壁。 该结构还包括位于半导体衬底内的第二金属半导体合金层，该第二金属半导体合金层位于该至少一个间隔物的覆盖区。 该结构还包括第一金属接触，其包含元素周期表第VIII族或第IB族的金属，以及位于第一金属半导体合金层上并自对准的W，B，P，Mo和Re中的至少一种 以及包含元素周期表第VIII族或第IB族的金属和第二金属半导体合金层自对准的W，B，P，Mo和Re中的至少一种的第二金属接触体。

    STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS
    8.
    发明申请
    STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS 有权
    创建完全自对准金属接触的结构和方法

    公开(公告)号：US20090174006A1

    公开(公告)日：2009-07-09

    申请号：US11970165

    申请日：2008-01-07

    申请人： Jeffery B. Maxson ,  Cung Do Tran ,  Huilong Zhu

    发明人： Jeffery B. Maxson ,  Cung Do Tran ,  Huilong Zhu

    IPC分类号： H01L29/78 ,  H01L21/4763

    CPC分类号： H01L29/7833 ,  H01L21/28052 ,  H01L21/288 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.

    摘要翻译： 提供具有完全自对准金属接触的半导体结构。 半导体结构包括位于半导体衬底的表面上的至少一个场效应晶体管。 所述至少一个场效应晶体管包括包括多晶硅的下层和第一金属半导体合金的上层的栅极导体堆叠，所述栅极导体堆叠具有包括至少一个间隔物的侧壁。 该结构还包括位于半导体衬底内的第二金属半导体合金层，该第二金属半导体合金层位于该至少一个间隔物的覆盖区。 该结构还包括第一金属接触，其包含元素周期表第VIII族或第IB族的金属，以及位于第一金属半导体合金层上并自对准的W，B，P，Mo和Re中的至少一种 以及包含元素周期表第VIII族或第IB族的金属和第二金属半导体合金层自对准的W，B，P，Mo和Re中的至少一种的第二金属接触体。

    Structure and method of creating entirely self-aligned metallic contacts
    9.
    发明授权
    Structure and method of creating entirely self-aligned metallic contacts 有权
    创建完全自对准的金属触点的结构和方法

    公开(公告)号：US07964923B2

    公开(公告)日：2011-06-21

    申请号：US11970165

    申请日：2008-01-07

    申请人： Jeffery B. Maxson ,  Cung Do Tran ,  Huilong Zhu

    发明人： Jeffery B. Maxson ,  Cung Do Tran ,  Huilong Zhu

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7833 ,  H01L21/28052 ,  H01L21/288 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.

    摘要翻译： 提供具有完全自对准金属接触的半导体结构。 半导体结构包括位于半导体衬底的表面上的至少一个场效应晶体管。 所述至少一个场效应晶体管包括包括多晶硅的下层和第一金属半导体合金的上层的栅极导体堆叠，所述栅极导体堆叠具有包括至少一个间隔物的侧壁。 该结构还包括位于半导体衬底内的第二金属半导体合金层，该第二金属半导体合金层位于该至少一个间隔物的覆盖区。 该结构还包括第一金属接触，其包含元素周期表第VIII族或第IB族的金属，以及位于第一金属半导体合金层上并自对准的W，B，P，Mo和Re中的至少一种 以及包含元素周期表第VIII族或第IB族的金属和第二金属半导体合金层自对准的W，B，P，Mo和Re中的至少一种的第二金属接触体。

    STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS
    10.
    发明申请
    STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS 有权
    创建完全自对准金属接触的结构和方法

    公开(公告)号：US20110237067A1

    公开(公告)日：2011-09-29

    申请号：US13155056

    申请日：2011-06-07

    申请人： Jeffery B. Maxson ,  Cung Do Tran ,  Huilong Zhu

    发明人： Jeffery B. Maxson ,  Cung Do Tran ,  Huilong Zhu

    IPC分类号： H01L21/768

    CPC分类号： H01L29/7833 ,  H01L21/28052 ,  H01L21/288 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.

    摘要翻译： 提供具有完全自对准金属接触的半导体结构。 半导体结构包括位于半导体衬底的表面上的至少一个场效应晶体管。 所述至少一个场效应晶体管包括包括多晶硅的下层和第一金属半导体合金的上层的栅极导体堆叠，所述栅极导体堆叠具有包括至少一个间隔物的侧壁。 该结构还包括位于半导体衬底内的第二金属半导体合金层，该第二金属半导体合金层位于该至少一个间隔物的覆盖区。 该结构还包括第一金属接触，其包含元素周期表第VIII族或第IB族的金属，以及位于第一金属半导体合金层上并自对准的W，B，P，Mo和Re中的至少一种 以及包含元素周期表第VIII族或第IB族的金属和第二金属半导体合金层自对准的W，B，P，Mo和Re中的至少一种的第二金属接触体。