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1.发明授权Method of forming silicide contacts of different shapes selectively on regions of a semiconductor device 有权在半导体器件的区域上选择性地形成不同形状的硅化物触点的方法公开(公告)号：US08415250B2
公开(公告)日：2013-04-09
申请号：US13097459
申请日：2011-04-29
申请人： Emre Alptekin , Dong-Ick Lee , Viraj Yashawant Sardesai , Cung Do Tran , Jian Yu , Reinaldo Ariel Vega , Rajasekhar Venigalla
发明人： Emre Alptekin , Dong-Ick Lee , Viraj Yashawant Sardesai , Cung Do Tran , Jian Yu , Reinaldo Ariel Vega , Rajasekhar Venigalla
IPC分类号： H01L29/417
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/76805 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L29/0847 , H01L29/66636 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.
摘要翻译： 提供了一种用于制造用于半导体器件的硅化物触点的结构和方法。 具体地，该结构和方法涉及利用化学气相沉积（CVD）和退火以在半导体场效应晶体管（FET）（例如源极和漏极区域）的区域上选择性地形成不同形状的硅化物接触。 硅化物触点的形状是可以被操纵以降低接触电阻的关键因素。 因此，该结构和方法提供具有低接触电阻的不同形状的硅化物触点，其中硅化物触点还减轻漏电流以增强低功率应用中的FET的效用和性能。
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2.发明申请METHOD OF FORMING SILICIDE CONTACTS OF DIFFERENT SHAPES SELECTIVELY ON REGIONS OF A SEMICONDUCTOR DEVICE 有权在半导体器件领域中选择形成不同形状的硅氧烷接触的方法公开(公告)号：US20120273798A1
公开(公告)日：2012-11-01
申请号：US13097459
申请日：2011-04-29
申请人： Emre Alptekin , Dong-Ick Lee , Viraj Yashawant Sardesai , Cung Do Tran , Jian Yu , Reinaldo Ariel Vega , Rajasekhar Venigalla
发明人： Emre Alptekin , Dong-Ick Lee , Viraj Yashawant Sardesai , Cung Do Tran , Jian Yu , Reinaldo Ariel Vega , Rajasekhar Venigalla
IPC分类号： H01L29/772
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/76805 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L29/0847 , H01L29/66636 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.
摘要翻译： 提供了一种用于制造用于半导体器件的硅化物触点的结构和方法。 具体地，该结构和方法涉及利用化学气相沉积（CVD）和退火以在半导体场效应晶体管（FET）（例如源极和漏极区域）的区域上选择性地形成不同形状的硅化物接触。 硅化物触点的形状是可以被操纵以降低接触电阻的关键因素。 因此，该结构和方法提供具有低接触电阻的不同形状的硅化物触点，其中硅化物触点还减轻漏电流以增强低功率应用中的FET的效用和性能。
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公开(公告)号：US08946081B2
公开(公告)日：2015-02-03
申请号：US13448497
申请日：2012-04-17
IPC分类号： H01L21/311 , H01L21/28 , H01L21/02 , H01L21/285 , H01L21/768
CPC分类号： H01L21/02068 , H01L21/02063 , H01L21/28518 , H01L21/76814
摘要： Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.
摘要翻译： 本发明的实施例包括清洁器件结构的半导体衬底的方法和在器件结构的半导体衬底上形成硅化物层的方法。 实施例包括将衬底的顶部转换成氧化物层并去除氧化物层以暴露衬底的无污染物表面的步骤。
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公开(公告)号：US20130273737A1
公开(公告)日：2013-10-17
申请号：US13448497
申请日：2012-04-17
IPC分类号： H01L21/02
CPC分类号： H01L21/02068 , H01L21/02063 , H01L21/28518 , H01L21/76814
摘要： Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.
摘要翻译： 本发明的实施例包括清洁器件结构的半导体衬底的方法和在器件结构的半导体衬底上形成硅化物层的方法。 实施例包括将衬底的顶部转换成氧化物层并去除氧化物层以暴露衬底的无污染物表面的步骤。
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5.发明授权Method of manufacturing dummy gates of a different material as insulation between adjacent devices 有权制造不同材料的虚拟栅极作为相邻器件之间绝缘的方法公开(公告)号：US09059308B2
公开(公告)日：2015-06-16
申请号：US13564792
申请日：2012-08-02
IPC分类号： H01L21/8238 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/49
CPC分类号： H01L21/823481 , H01L21/823437 , H01L21/823828 , H01L27/088 , H01L29/49 , H01L29/66545
摘要： Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.
摘要翻译： 本发明的实施例包括由不同材料的虚拟栅极隔开的两个晶体管结构的半导体结构和用于形成所述结构的方法。 实施例包括在半导体衬底上形成牺牲栅极，在牺牲栅上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源/漏区，以及用绝缘材料代替第三牺牲栅。 替代第三牺牲栅极的绝缘材料可以用作虚拟栅极以电隔离附近的源极/漏极区域。 实施例还包括在半导体衬底上形成牺牲栅极，在牺牲栅极上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源极/漏极区域，并且在离开第三牺牲栅极的同时用金属栅极替换两个牺牲栅极 到位作为虚拟门。
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6.发明申请Method of Manufacturing Dummy Gates of a Different Material as Insulation between Adjacent Devices 有权制造不同材料的虚拟门的方法作为相邻设备之间的绝缘公开(公告)号：US20140035045A1
公开(公告)日：2014-02-06
申请号：US13564792
申请日：2012-08-02
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/823481 , H01L21/823437 , H01L21/823828 , H01L27/088 , H01L29/49 , H01L29/66545
摘要： Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.
摘要翻译： 本发明的实施例包括由不同材料的虚拟栅极隔开的两个晶体管结构的半导体结构和用于形成所述结构的方法。 实施例包括在半导体衬底上形成牺牲栅极，在牺牲栅上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源/漏区，以及用绝缘材料代替第三牺牲栅。 替代第三牺牲栅极的绝缘材料可以用作虚拟栅极以电隔离附近的源极/漏极区域。 实施例还包括在半导体衬底上形成牺牲栅极，在牺牲栅极上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源极/漏极区域，并且在离开第三牺牲栅极的同时用金属栅极替换两个牺牲栅极 到位作为虚拟门。
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公开(公告)号：US20120112290A1
公开(公告)日：2012-05-10
申请号：US12942097
申请日：2010-11-09
申请人： Henry K. Utomo , Unoh Kwon , Dimitri Anastassios Levedakis , Ravikumar Ramachandran , Viraj Yashawant Sardesai , Rajasekhar Venigalla
发明人： Henry K. Utomo , Unoh Kwon , Dimitri Anastassios Levedakis , Ravikumar Ramachandran , Viraj Yashawant Sardesai , Rajasekhar Venigalla
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/823814 , H01L21/823842 , H01L21/823871 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.
摘要翻译： 公开了一种替代金属栅极（RMG）场效应晶体管的结构和方法。 硅化物区域形成在升高的源极 - 漏极（RSD）结构上。 硅化物区域在用于在更换之前暴露栅极的CMP工艺期间形成化学机械抛光（CMP）停止层。 然后在金属触点的形成中施加和蚀刻保护层。
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8.发明授权公开(公告)号：US08420491B2
公开(公告)日：2013-04-16
申请号：US12942097
申请日：2010-11-09
申请人： Henry K. Utomo , Unoh Kwon , Dimitri Anastassios Levedakis , Ravikumar Ramachandran , Viraj Yashawant Sardesai , Rajasekhar Venigalla
发明人： Henry K. Utomo , Unoh Kwon , Dimitri Anastassios Levedakis , Ravikumar Ramachandran , Viraj Yashawant Sardesai , Rajasekhar Venigalla
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/823814 , H01L21/823842 , H01L21/823871 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.
摘要翻译： 公开了一种替代金属栅极（RMG）场效应晶体管的结构和方法。 硅化物区域形成在升高的源极 - 漏极（RSD）结构上。 硅化物区域在用于在更换之前暴露栅极的CMP工艺期间形成化学机械抛光（CMP）停止层。 然后在金属触点的形成中施加和蚀刻保护层。
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公开(公告)号：US08420542B2
公开(公告)日：2013-04-16
申请号：US13117208
申请日：2011-05-27
IPC分类号： H01L21/311
CPC分类号： H01L21/0337
摘要： A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern.
摘要翻译： 公开了一种在半导体基底层上形成反向图案的方法。 该方法包括在半导体基底层上沉积无定形碳的转移层，在转移层上沉积抗蚀剂层，在抗蚀剂层中产生第一图案，在转移层中产生第一图案，去除抗蚀剂层，沉积 反面掩模层，平面化反掩膜层，以及去除转印层，从而形成作为第一图案的反转图像的第二图案。
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公开(公告)号：US20120302069A1
公开(公告)日：2012-11-29
申请号：US13117208
申请日：2011-05-27
IPC分类号： H01L21/311 , B82Y40/00
CPC分类号： H01L21/0337
摘要： A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern.
摘要翻译： 公开了一种在半导体基底层上形成反向图案的方法。 该方法包括在半导体基底层上沉积无定形碳的转移层，在转移层上沉积抗蚀剂层，在抗蚀剂层中产生第一图案，在转移层中产生第一图案，去除抗蚀剂层，沉积 反面掩模层，平面化反掩膜层，以及去除转印层，从而形成作为第一图案的反转图像的第二图案。
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