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公开(公告)号：US6084934A
公开(公告)日：2000-07-04
申请号：US811776
申请日：1997-03-06
CPC分类号： H04L7/0008 , G06F5/06 , H04L25/4904
摘要： A data transmission system includes a sender and a receiver, both employing different clock rates and a data bus coupled between the sender and the receiver for transmitting signals therebetween. The receiver generates an enable signal from the receiver clock to control data transmission at the sender. The enable signal is a pulse generated at each rising edge of the receiver clock and corresponds to the data transfer rate of the receiver clock. A detector module, located at the sender, receives and captures the asynchronous enable signal and initiates transmission of one data byte for each pulse of the enable signal, thereby automatically adjusting the data transfer rate of the sender to the data transfer rate of the receiver.
摘要翻译： 数据传输系统包括发送器和接收器，它们采用不同的时钟速率，耦合在发送器和接收器之间的数据总线用于在它们之间传输信号。 接收机从接收器时钟产生使能信号以控制发送器处的数据传输。 使能信号是在接收机时钟的每个上升沿产生的脉冲，对应于接收机时钟的数据传送速率。 位于发送器处的检测器模块接收并捕获异步使能信号，并启动对使能信号的每个脉冲的一个数据字节的传输，从而自动将发送器的数据传输速率调整到接收机的数据传输速率。
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公开(公告)号：US06581141B1
公开(公告)日：2003-06-17
申请号：US09314045
申请日：1999-05-18
IPC分类号： G06F1316
CPC分类号： G06F13/4059
摘要： A system and method for optimally processing split request transactions across a PCI-X bridge with a PCI-X bridge buffer. The split transaction mode of the PCI-X bridge buffer is toggled between a No Over-commit mode and an over-commit mode. Over-commitment of the buffer is inhibited when the split transaction mode is toggled to the No Over-commit mode and when the buffer is over committed by the bridge. At least some over-commitment of the buffer is allowed by the bridge when the split transaction mode is toggled to the over-commit mode and when the buffer is not over committed by the bridge. The over-commit mode may be an Over-commitment mode or a Flood mode. The Over-commitment mode allows some degree of over commitment of the buffer by the bridge while the Flood mode allows the bridge to forward all split request transactions regardless of size of the transactions or amount of available space in the buffer when the Over-commit mode is in a Flood mode. The split request transaction is controlled and forwarded based on the toggled split transaction mode. The system comprises at least a toggle switch and a control system. The split transaction mode is toggled to or maintained at a particular mode based on whether a retry or disconnect of the split completion transaction by the PCI-X bridge has or has not occurred and whether the buffer is or is not over committed.
摘要翻译： 一种用于通过PCI-X桥接缓冲区优化处理跨PCI-X网桥的分离请求事务的系统和方法。 PCI-X桥接缓冲区的拆分事务模式在无提交模式和过度提交模式之间切换。 当分割事务模式切换到“否”超过提交模式时，以及缓冲区由桥接器过渡时，缓冲区的过度承诺将被禁止。 当分裂事务模式切换到过度提交模式时，并且缓冲区未超过桥接器时，桥接器允许缓冲区的至少一些过度承诺。 过度提交模式可能是过度承诺模式或洪水模式。 过度承诺模式允许桥接器缓冲区过度承担一定程度，而洪泛模式允许桥接器转发所有拆分请求事务，而不管事务的大小或缓冲区中的可用空间量，当过度提交模式 处于泛洪模式。 分割请求事务基于切换的分组事务模式进行控制和转发。 该系统至少包括拨动开关和控制系统。 基于PCI-X网桥的分裂完成事务的重试或断开是否已经发生或者没有发生以及缓冲器是否还未被提交，分割事务模式被切换到或维持在特定模式。
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3.发明授权Split completion performance of PCI-X bridges based on data transfer amount 失效基于数据传输量分割PCI-X网桥的完成性能公开(公告)号：US06957293B2
公开(公告)日：2005-10-18
申请号：US10122989
申请日：2002-04-15
CPC分类号： G06F13/4027
摘要： Embodiments are provided in which a method is described for transferring data in a digital system including a first bus, a second bus, a PCI-X bridge coupling the first and second buses, and a first device and a second device residing on the first and second buses, respectively. The first bus has the same or higher bandwidth than that of the second bus. According to the method, the PCI-X bridge immediately starts or resumes forwarding split completion data from the first device to the second device if the first device starts or resumes split completion data transfer to the PCI-X bridge at the beginning of a block (i.e., the start or resume byte address has the form of 128N). If the first device starts transfer to the PCI-X bridge not at the beginning of a block, the PCI-X bridge refrains from forwarding split completion data until (a) the first device sends the data byte at the beginning of the next block to the PCI-X bridge or (b) the byte transfer count is exhausted, whichever occurs first.
摘要翻译： 提供了一种描述用于在包括第一总线，第二总线，耦合第一和第二总线的PCI-X桥接器的数字系统中传送数据的方法以及驻留在第一总线上的第一设备和第二设备， 第二辆巴士。 第一条总线具有与第二条总线相同或更高的带宽。 根据该方法，如果第一设备在块开始时启动或恢复到PCI-X桥接器的分离完成数据传输，则PCI-X桥立即启动或恢复从第一设备转发分组完成数据到第二设备（ 即，起始或恢复字节地址的形式为128N）。 如果第一个设备开始传输到不在块开始处的PCI-X网桥，则PCI-X网桥不会转发分组完成数据，直到（a）第一个设备将下一个块开头的数据字节发送到 PCI-X网桥或（b）字节传输计数用尽，以先到者为准。
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公开(公告)号：US06766405B2
公开(公告)日：2004-07-20
申请号：US10109425
申请日：2002-03-28
IPC分类号： G06F1320
CPC分类号： G06F11/0751 , G06F11/0745 , G06F11/079 , G06F13/4059
摘要： A split operation such as a split read or a split write is handled by a bus bridge circuit. The bus bridge receives the read or write command from a requesting device, where the command includes a bus number for routing a completion of the command. The bus bridge then compares the bus number received from the requesting device with the return route bus number range of the bus bridge, and issues a split response to the requesting device if the bus number matches the return route bus number range of the bus bridge. If the bus number does not match the return route bus number range, then the command is aborted.
摘要翻译： 诸如分离读取或分离写入的分离操作由总线桥接电路来处理。 总线桥从请求设备接收读或写命令，其中命令包括用于路由命令完成的总线号。 然后，总线桥将从请求设备接收的总线号与总线桥的返回路由总线编号范围进行比较，并且如果总线号与总线桥的返回路由总线数范围匹配，则向请求设备发出分离响应。 如果总线编号与返回路由总线编号范围不匹配，则命令将中止。
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5.发明授权Performance enhancement implementation through buffer management/bridge settings 有权通过缓冲管理/桥设置实现性能提升公开(公告)号：US06665753B1
公开(公告)日：2003-12-16
申请号：US09637317
申请日：2000-08-10
IPC分类号： G06F300
CPC分类号： G06F13/4059
摘要： A method, system, and apparatus for modifying bridges within a data processing system to provide improved performance is provided. In one embodiment, the data processing system determines the number of input/output adapters connected underneath each PCI host bridge. The data processing system also determines the type of each input/output adapter. The size and number of buffers within the PCI host bridge is then modified based on the number of adapters beneath it as well as the type of adapters beneath it to improve data throughput performance as well as prevent thrashing of data. The PCI host bridge is also modified to give load and store operations priority over DMA operations. Each PCI-to-PCI bridge is modified based on the type of adapter connected to it such that the PCI-to-PCI bridge prefetches only an amount of data consistent with the type of adapter such that excess data is not thrashed, thus requiring extensive repetitive use of the system buses to retrieve the same data more than once.
摘要翻译： 提供了一种用于修改数据处理系统内的网桥以提供改进性能的方法，系统和装置。 在一个实施例中，数据处理系统确定在每个PCI主机桥下面连接的输入/输出适配器的数量。 数据处理系统还确定每个输入/输出适配器的类型。 然后，PCI主机桥中的缓冲区的大小和数量将根据其下的适配器数量以及其下的适配器类型进行修改，以提高数据吞吐量性能，并防止数据崩溃。 还修改了PCI主机桥，以使加载和存储操作优先于DMA操作。 每个PCI到PCI桥接器根据连接到它的适配器的类型进行修改，以使PCI-PCI桥只预取与适配器类型一致的数据量，以使得多余的数据不会被捶打，因此需要大量的 重复使用系统总线多次检索相同的数据。
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公开(公告)号：US06519718B1
公开(公告)日：2003-02-11
申请号：US09506783
申请日：2000-02-18
IPC分类号： H04L124
CPC分类号： H04L1/24 , G06F11/221
摘要： A method and apparatus are provided for implementing error injection for peripheral component interconnect (PCI) bridges. The apparatus for implementing error injection for peripheral component interconnect (PCI) bridges includes a plurality of PCI busses and a control logic coupled to the plurality of PCI busses. The control logic targets a selected bus of the plurality of PCI busses. A hit is detected on the selected bus. Responsive to the detected hit, an error is injected on the selected bus. For a detected hit for predefined bug types, the operation must match a selected read or write, target or master, command type and the address must match unmasked address bits. For a detected hit for another predefined bug type, the PCI data bus must also match an unmask data register.
摘要翻译： 提供了一种用于实现外围组件互连（PCI）桥的错误注入的方法和装置。 用于实现外围组件互连（PCI）桥的错误注入的装置包括多个PCI总线和耦合到多个PCI总线的控制逻辑。 控制逻辑针对多个PCI总线的选定总线。 在所选择的总线上检测到命中。 响应于检测到的命中，在所选择的总线上注入错误。 对于检测到的预定义错误类型的命中，操作必须匹配所选的读取或写入，目标或主机命令类型，并且地址必须与未屏蔽的地址位匹配。 对于另一预定义的错误类型的检测到的命中，PCI数据总线也必须与取消掩码数据寄存器匹配。
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公开(公告)号：US06581129B1
公开(公告)日：2003-06-17
申请号：US09414339
申请日：1999-10-07
申请人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
发明人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
IPC分类号： G06F1336
CPC分类号： G06F13/4027
摘要： A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.
摘要翻译： 公开了PCI主机桥和相关联的使用方法。 PCI主机桥包括主机总线接口，I / O总线接口和PCI操作检测电路。 主机总线接口适用于与数据处理系统的主机总线进行通信，I / O总线接口适用于与PCI-X模式下工作的主PCI总线进行通信。 PCI操作检测电路适于检测可能从耦合到辅助PCI总线的PCI模式适配器发出的主PCI总线的PCI-X操作。 检测电路还适于响应于确定PCI-X操作可能源自于PCI而产生用于转发到主机总线的修改操作。 模式适配器。
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8.发明授权System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer 有权即使当前信息传送请求超过传送缓冲器的当前可用容量时，也执行当前信息传送请求的系统公开(公告)号：US06457077B1
公开(公告)日：2002-09-24
申请号：US09329459
申请日：1999-06-10
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit to, transaction requests from system devices for information transfers which exceed the bridge circuit's current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an example, to the requesting device. By the time the requested information is returned to the requesting bridge circuit, a number of the holding buffers usually have been freed-up and are available to accept and pass the information to the requesting device. In an illustrated embodiment, the amount of over-commitment is programmable and the amount of over-commitment to transaction requests may be automatically adjusted to optimize the information transfer in accordance with the particular system demands and current data transfer traffic levels.
摘要翻译： 提供了一种方法和实现系统，其中系统桥电路能够执行或过度提交来自用于信息传输的系统设备的事务请求，该信息传输超过桥电路的当前容量，以便在从指定目标返回时接收所请求的信息 设备如系统内存或其他系统设备。 交易请求沿着数据路径移动到指定的目标设备，并且所请求的信息在示例中返回到请求设备。 当所请求的信息被返回到请求桥接电路时，多个保持缓冲器通常已经被释放并且可用于接受并将该信息传递给请求设备。 在所示实施例中，过度承诺的量是可编程的，并且可以自动调整对交易请求的过度承诺的量，以根据特定系统需求和当前数据传输流量水平优化信息传递。
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公开(公告)号：US5918242A
公开(公告)日：1999-06-29
申请号：US805095
申请日：1997-02-24
CPC分类号： G06F11/1044 , G06F12/0848 , G06F12/0893 , G06F13/1694 , G06F11/1056
摘要： A memory controller design includes at least one memory instruction decoder de-embedded from a memory instruction processor wherein the memory instruction processor receives operations and logical address information from a host processor. The memory instruction processor converts the operations into generic memory instructions and translates the logical addresses into physical addresses. The memory instruction decoder further converts the generic memory instructions into memory specific control signals and converts the physical addresses into actual memory specific addresses. This design permits the memory instruction processor to be designed and finalized before an actual memory type is selected for system use at which time the less complex memory instruction decoder can be designed.
摘要翻译： 存储器控制器设计包括从存储器指令处理器去嵌入的至少一个存储器指令解码器，其中存储器指令处理器从主处理器接收操作和逻辑地址信息。 存储器指令处理器将操作转换成通用存储器指令，并将逻辑地址转换为物理地址。 存储器指令解码器还将通用存储器指令转换为存储器特定控制信号，并将物理地址转换成实际的存储器特定地址。 该设计允许在为系统使用选择实际的存储器类型之前设计和确定存储器指令处理器，此时可以设计较不复杂的存储器指令解码器。
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10.发明授权Synchronous DRAM controller with memory access commands timed for optimized use of data bus 失效具有存储器访问命令的同步DRAM控制器定时用于优化数据总线的使用
公开(公告)号：US5684978A
公开(公告)日：1997-11-04
申请号：US545975
申请日：1995-10-20
CPC分类号： G06F13/161
摘要： For an synchronous dynamic access memory ("S-DRAM") system including a memory assembly with multiple memory units, data access commands are placed on a command bus at specific times to facilitate gapless data bus operation. After receipt of a first memory access request, a first memory access command is issued on the command bus to exchange a first data string having a first length with a first one of the memory units. Subsequently, receipt occurs of a second memory access request is to exchange a second data string, of a second length, with a second one of the memory units. A determination is made of an earliest possible time for placement of a second memory access command upon the command bus; this considers various factors, such as the first length, data bus availability, command bus availability, and any predetermined delay in placement of the first data string onto the data bus. Accordingly, the second memory access command is placed upon the command bus at the determined time. After the first data string leaves the data bus, any exchange of data between the first memory unit and the data bus may be prevented for a predetermined time.
摘要翻译： 对于包括具有多个存储器单元的存储器组件的同步动态存取存储器（“S-DRAM”）系统，在特定时刻将数据访问命令放置在命令总线上，以便于无间隙数据总线操作。 在接收到第一存储器访问请求之后，在命令总线上发出第一存储器访问命令，以将具有第一长度的第一数据串与存储器单元中的第一个进行交换。 随后，第二存储器访问请求的接收发生是与第二个存储器单元交换具有第二长度的第二数据串。 确定在命令总线上放置第二存储器访问命令的最早可能的时间; 这考虑了诸如第一长度，数据总线可用性，命令总线可用性以及将第一数据串放置到数据总线上的任何预定延迟的各种因素。 因此，第二存储器访问命令在确定的时间被放置在命令总线上。 在第一数据串离开数据总线之后，可以在预定时间内防止第一存储器单元和数据总线之间的任何数据交换。
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