公开(公告)号：US06925547B2

公开(公告)日：2005-08-02

申请号：US10017488

申请日：2001-12-14

申请人： Steven L. Scott ,  Chris Dickson ,  Eric C. Fromm ,  Michael L. Anderson

发明人： Steven L. Scott ,  Chris Dickson ,  Eric C. Fromm ,  Michael L. Anderson

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1072 ,  G06F12/1027

摘要： A method of performing remote address translation in a multiprocessor system includes determining a connection descriptor and a virtual address at a local node, accessing a local connection table at the local node using the connection descriptor to produce a system node identifier for a remote node and a remote address space number, communicating the virtual address and remote address space number to the remote node, and translating the virtual address to a physical address at the remote node (qualified by the remote address space number). A user process running at the local node provides the connection descriptor and virtual address. The translation is performed by matching the virtual address and remote address space number with an entry of a translation-lookaside buffer (TLB) at the remote node. Performing the translation at the remote node reduces the amount of translation information needed at the local node for remote memory accesses. The method supports communication within a scalable multiprocessor, and across the machine boundaries in a cluster.

摘要翻译： 在多处理器系统中执行远程地址转换的方法包括确定本地节点处的连接描述符和虚拟地址，使用连接描述符访问本地节点处的本地连接表，以产生远程节点的系统节点标识符，以及 远程地址空间号码，将虚拟地址和远程地址空间号码传送到远程节点，并将虚拟地址转换为远程节点的物理地址（由远程地址空间号限定）。 在本地节点运行的用户进程提供连接描述符和虚拟地址。 通过将虚拟地址和远程地址空间编号与远程节点上的翻译后备缓冲区（TLB）的条目进行匹配来执行翻译。 在远程节点执行翻译可减少本地节点为远程存储器访问所需的翻译信息量。 该方法支持可扩展多处理器内的通信，并支持集群中的机器边界。

公开(公告)号：US06604185B1

公开(公告)日：2003-08-05

申请号：US09619851

申请日：2000-07-20

申请人： Eric C. Fromm

发明人： Eric C. Fromm

IPC分类号： G06F1212

CPC分类号： G06F12/1072 ,  G06F12/1027 ,  G06F2212/682

摘要： A method and apparatus for deallocating memory in a multi-processor, shared memory system. In one aspect, a node in the system has a node controller that contains sequencing logic. The sequencing logic receives a command across a network. The sequencing logic translates the received command into a Purge Translation Cache (PTC) instruction and sends the PTC instruction across a bus to a processor. The processor contains bus control logic that receives the PTC instruction and purges a virtual address specified in the PTC instruction from the processor's translation lookaside buffer. By purging the virtual address, the memory is deallocated.

摘要翻译： 一种用于在多处理器共享存储器系统中释放存储器的方法和装置。 在一个方面，系统中的节点具有包含排序逻辑的节点控制器。 排序逻辑通过网络接收命令。 排序逻辑将接收到的命令转换为清除转换缓存（PTC）指令，并将总线上的PTC指令发送到处理器。 该处理器包含总线控制逻辑，接收PTC指令，并从处理器的转换后备缓冲器清除PTC指令中指定的虚拟地址。 通过清除虚拟地址，释放内存。

公开(公告)号：US6119198A

公开(公告)日：2000-09-12

申请号：US889251

申请日：1997-07-08

申请人： Eric C. Fromm

发明人： Eric C. Fromm

IPC分类号： G06F7/76 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80 ,  G06F12/04 ,  G06F5/01

CPC分类号： G06F15/8007 ,  G06F12/0692 ,  G06F15/17381 ,  G06F7/762

摘要： A method for extracting a PE number and offset from an array index by recursive centrifuging. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in a multidimensional array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a mask word determined from the distribution specification associated with the array. The mask word is generated from the distribution specification and applied to a linearized index associated with a particular array element to obtain processing element number bits and local offset bits. The processing element number bits and local offset bits are then accumulated to create the processing element number and local offset for the memory location associated with the array element.

摘要翻译： 通过递归离心提取PE数和从数组索引偏移的方法。 根据本发明的一个方面，处理单元编号被分配给每个处理单元，将局部存储器地址分配给每个存储器单元，并且线性化索引被分配给多维阵列中的每个阵列元素。 作为与阵列元素相关联的线性化索引和从与阵列相关联的分布规范确定的掩码字的函数来计算其中存储特定数组元素的处理元件的处理元件号。 掩模字从分布规范生成并应用于与特定数组元素相关联的线性化索引，以获得处理元素数位和局部偏移位。 然后累积处理元件数位和局部偏移位以产生与数组元素相关联的存储器位置的处理元件号和本地偏移。

公开(公告)号：US20090222821A1

公开(公告)日：2009-09-03

申请号：US12039048

申请日：2008-02-28

申请人： Eric C. Fromm ,  Gregory M. Thorson

发明人： Eric C. Fromm ,  Gregory M. Thorson

IPC分类号： G06F9/50

CPC分类号： G06F9/5016 ,  G06F2209/5021

摘要： Processing transaction requests in a shared memory multi-processor computer network is described. A transaction request is received at a servicing agent from a requesting agent. The transaction request includes a request priority associated with a transaction urgency generated by the requesting agent. The servicing agent provides an assigned priority to the transaction request based on the request priority, and then compares the assigned priority to an existing service level at the servicing agent to determine whether to complete or reject the transaction request. A reply message from the servicing agent to the requesting agent is generated to indicate whether the transaction request was completed or rejected, and to provide reply fairness state data for rejected transaction requests.

摘要翻译： 描述在共享存储器多处理器计算机网络中处理事务请求。 在请求代理处的服务代理处接收到交易请求。 交易请求包括与请求代理产生的事务紧急性相关联的请求优先级。 服务代理根据请求优先级为交易请求提供分配的优先级，然后将分配的优先级与服务代理处的现有服务级别进行比较，以确定是否完成或拒绝交易请求。 产生从服务代理到请求代理的回复消息，以指示交易请求是否已完成或拒绝，并为拒绝的交易请求提供回复公平状态数据。

公开(公告)号：US06839856B1

公开(公告)日：2005-01-04

申请号：US09620058

申请日：2000-07-20

申请人： Eric C. Fromm ,  Rodney Ruesch

发明人： Eric C. Fromm ,  Rodney Ruesch

IPC分类号： G06F13/12 ,  G06F13/42

CPC分类号： G06F13/124

摘要： A bus interface circuit and method for reliable data capture in the presence of bus-master changeovers and/or for synchronizing received data to an internal clock signal, wherein the received data includes a strobe. Since the strobe may have a delay that is unknown (due to varying distances from the driver, clock jitter, and/or other causes), it is important to re-synchronize to the internal clock, and to do so with the smallest delay possible. This synchronization is provided in a way that also eliminates potential problems due to bus-master changeover, and in a way that minimizes time-critical signal generation. One aspect provides a method and/or apparatus for reliable data capture. The method includes: providing an N-stage latch including a first stage latch and a second stage latch, wherein N is two or larger; loading every Nth word of a data stream into the first stage latch using a first signal based on a strobe passed in the data stream; loading every N+1st word of the data stream into the second stage latch using a second signal based on the strobe passed in the data stream; unloading every Nth word from the first stage latch using a third signal based on an internal bus clock; and unloading every N+1st word from the second stage latch using a fourth signal based on the internal bus clock. In some embodiments, the first signal and the second signal are further based on a first stage selector and on a data_ready signal passed in the data stream.

摘要翻译： 一种总线接口电路和方法，用于在存在总线主机切换和/或用于将接收到的数据同步到内部时钟信号的情况下可靠地进行数据采集，其中所接收的数据包括选通脉冲。 由于选通可能具有未知的延迟（由于与驱动器的距离不同，时钟抖动和/或其他原因），因此重要的是重新同步到内部时钟，并以尽可能小的延迟 。 以同样的方式提供同步，这也消除了由于总线主机切换引起的潜在问题，并以最小化时间关键信号产生的方式。 一方面提供了用于可靠数据捕获的方法和/或装置。 该方法包括：提供包括第一级锁存器和第二级锁存器的N级锁存器，其中N为两个或更大; 使用基于在数据流中传递的选通脉冲的第一信号将数据流的每第N个字加载到第一级锁存器中; 使用基于在数据流中传递的选通脉冲的第二信号将数据流的每个N + 1个字加载到第二级锁存器中; 使用基于内部总线时钟的第三信号从第一级锁存器卸载第N个字; 并且使用基于内部总线时钟的第四信号从第二级锁存器卸载每个N + 1个字。 在一些实施例中，第一信号和第二信号还基于第一级选择器和在数据流中传递的data_ready信号。

公开(公告)号：US5835925A

公开(公告)日：1998-11-10

申请号：US615671

申请日：1996-03-13

申请人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Eric C. Fromm

发明人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Eric C. Fromm

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/355 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F9/342 ,  G06F12/0292 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3861

摘要： A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.

摘要翻译： 一种访问具有处理器和与处理器分离的多个存储器位置的系统内的存储器位置的系统和方法。 该系统包括通过数据总线连接到处理器的多个外部寄存器，通过数据总线连接到处理器的地址转换装置和地址总线，用于基于写入数据总线的索引来计算 连接到多个外部寄存器的传送装置，用于在寻址的存储器位置和外部寄存器之一之间传送数据。

公开(公告)号：US07587305B2

公开(公告)日：2009-09-08

申请号：US10180265

申请日：2002-06-26

申请人： Robert J. Lutz ,  Mark S. Birrittella ,  Eric C. Fromm ,  Harro Zimmermann

发明人： Robert J. Lutz ,  Mark S. Birrittella ,  Eric C. Fromm ,  Harro Zimmermann

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5036

摘要： A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a second leaf cell in Verilog syntax. A connection between the first leaf cell and the second leaf cell is also specified in Verilog syntax. This specifies a circuit. The functionality of the logic can be tested by running a logic simulation on the circuit without converting to Verilog syntax. The Verilog syntax, associated with the circuit, can be converted directly from Verilog syntax to a SPICE netlist. The SPICE netlist can be used to simulate the timing and other parameters of the circuit. The Verilog syntax can be used to verify the circuit. Also included are a computer readable medium including an instruction set for the above method, and a data structure necessary to carry out the above method.

摘要翻译： 一种方法包括在Verilog语法中指定与第一叶单元相关联的第一组互连设备，以及在Verilog语法中指定与第二叶单元相关联的第二组互连设备。 在Verilog语法中也指定了第一个叶单元和第二个叶单元之间的连接。 这指定一个电路。 可以通过在电路上运行逻辑仿真而不转换为Verilog语法来测试逻辑的功能。 与电路相关的Verilog语法可以直接从Verilog语法转换为SPICE网表。 SPICE网表可用于模拟电路的时序和其他参数。 Verilog语法可用于验证电路。 还包括包括用于上述方法的指令集的计算机可读介质，以及执行上述方法所需的数据结构。

公开(公告)号：US6029212A

公开(公告)日：2000-02-22

申请号：US6449

申请日：1998-01-13

申请人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Eric C. Fromm

发明人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Eric C. Fromm

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/355 ,  G06F12/02 ,  G06F13/14 ,  G06F15/163

CPC分类号： G06F9/342 ,  G06F12/0292 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3861

摘要： A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.

摘要翻译： 一种访问具有处理器和与处理器分离的多个存储器位置的系统内的存储器位置的系统和方法。 该系统包括通过数据总线连接到处理器的多个外部寄存器，通过数据总线连接到处理器的地址转换装置和地址总线，用于基于写入数据总线的索引来计算 连接到多个外部寄存器的传送装置，用于在寻址的存储器位置和外部寄存器之一之间传送数据。

公开(公告)号：US5696922A

公开(公告)日：1997-12-09

申请号：US165388

申请日：1993-12-10

申请人： Eric C. Fromm

发明人： Eric C. Fromm

IPC分类号： G06F7/76 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80 ,  G06F12/00

CPC分类号： G06F15/8007 ,  G06F12/0692 ,  G06F15/17381 ,  G06F7/762

摘要： A method for extracting a PE number and offset from an array index by recursive centrifuging. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in a multidimensional array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a mask word determined from the distribution specification associated with the array. The mask word is generated from the distribution specification and applied to a linearized index associated with a particular array element to obtain processing element number bits and local offset bits. The processing element number bits and local offset bits are then accumulated to create the processing element number and local offset for the memory location associated with the array element.

摘要翻译： 通过递归离心提取PE数和从数组索引偏移的方法。 根据本发明的一个方面，处理单元编号被分配给每个处理单元，将局部存储器地址分配给每个存储器单元，并且线性化索引被分配给多维阵列中的每个阵列元素。 作为与阵列元素相关联的线性化索引和从与阵列相关联的分布规范确定的掩码字的函数来计算其中存储特定数组元素的处理元件的处理元件号。 掩模字从分布规范生成并应用于与特定数组元素相关联的线性化索引，以获得处理元素数位和局部偏移位。 然后累积处理元件数位和局部偏移位以产生与数组元素相关联的存储器位置的处理元件号和本地偏移。

公开(公告)号：US5592487A

公开(公告)日：1997-01-07

申请号：US407808

申请日：1995-03-20

申请人： Kevin M. Knecht ,  Eric C. Fromm

发明人： Kevin M. Knecht ,  Eric C. Fromm

IPC分类号： H04L25/49 ,  H04J3/24

CPC分类号： H04L25/4906

摘要： A communications protocol having a plurality of signals, wherein the plurality of signals includes data packets, control packets, checksum packets and sync symbols. One of the control packets is transmitted after a sync symbol is transmitted. One of the sync symbols, data packets or checksum packets is transmitted after the control packet is transmitted. One of the sync symbols is transmitted after one of said checksum packets is transmitted and one of the sync symbols or another of the data packets is transmitted after one of the data packets is transmitted.

摘要翻译： 一种具有多个信号的通信协议，其中所述多个信号包括数据分组，控制分组，校验和分组和同步符号。 在发送同步符号之后发送控制分组之一。 在发送控制分组之后发送同步符号，数据分组或校验和分组之一。 在发送所述校验和分组之一之后发送其中一个同步符号，并且在发送数据分组之一之后发送其中一个同步符号或另一个数据分组。