公开(公告)号：US20150103389A1

公开(公告)日：2015-04-16

申请号：US14401081

申请日：2013-05-24

申请人： Erich R. Klawuhn ,  Dhairya Shrivastava ,  Trevor Frank ,  Victor Beylin ,  Stephen C. Brown ,  Todd Martin ,  Robin Friedman

发明人： Erich R. Klawuhn ,  Dhairya Shrivastava ,  Trevor Frank ,  Victor Beylin ,  Stephen C. Brown ,  Todd Martin ,  Robin Friedman

IPC分类号： G02F1/163 ,  E06B9/24

CPC分类号： G02F1/163 ,  E06B9/24 ,  E06B2009/2464 ,  G02F1/15

摘要： A portable controller having a portable power supply for transitioning tint of an optical device such as an electrochromic device. The portable power supply has at least one battery located within a housing and a support structure for supporting the battery. The portable controller has circuitry with logic for controlling power to the optical device. In some cases, the portable power supply may provide a higher than normal drive voltage to the optical device to accelerate transition to the tint state and then may reduce the drive voltage to a normal level.

摘要翻译： 一种便携式控制器，其具有用于转换诸如电致变色装置的光学装置的着色的便携式电源。 便携式电源具有位于壳体内的至少一个电池和用于支撑电池的支撑结构。 便携式控制器具有用于控制光学装置的功率的逻辑电路。 在一些情况下，便携式电源可以向光学装置提供高于正常的驱动电压，以加速转变到色调状态，然后可将驱动电压降低到正常水平。

公开(公告)号：US06905959B1

公开(公告)日：2005-06-14

申请号：US10335464

申请日：2002-12-31

申请人： Kaihan A. Ashtiani ,  Maximilian A. Biberger ,  Erich R. Klawuhn ,  Kwok Fai Lai ,  Karl B. Levy ,  J. Patrick Rymer

发明人： Kaihan A. Ashtiani ,  Maximilian A. Biberger ,  Erich R. Klawuhn ,  Kwok Fai Lai ,  Karl B. Levy ,  J. Patrick Rymer

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76873 ,  H01L21/76876

摘要： A method of depositing thin films comprising tantalum, tantalum nitride, and copper for barrier films and seed layers within high aspect ratio openings used for copper interconnects. The barrier films and seed layers are deposited at extremely low temperature conditions wherein the wafer stage temperature of the sputter source is chilled to about −70° C. to about 0° C. Most preferably, the present invention is practiced using a hollow cathode magnetron. The resulting tantalum and/or tantalum nitride barrier films and copper seed layers are superior in surface smoothness, grain size and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.

摘要翻译： 一种用于在用于铜互连的高纵横比开口中沉积用于阻挡膜和种子层的钽，氮化钽和铜的薄膜的方法。 阻挡膜和种子层在极低温度条件下沉积，其中溅射源的晶片台温度被冷却至约-70℃至约0℃。最优选地，本发明使用空心阴极磁控管 。 所得到的钽和/或氮化钽阻挡膜和铜籽晶层的表面平滑度，晶粒尺寸和均匀性都是优异的，使得高纵横比开口的后续填充基本上无空隙。

公开(公告)号：US08858763B1

公开(公告)日：2014-10-14

申请号：US12391719

申请日：2009-02-24

申请人： Erich R. Klawuhn ,  Robert Rozbicki ,  Girish A. Dixit

发明人： Erich R. Klawuhn ,  Robert Rozbicki ,  Girish A. Dixit

IPC分类号： C23C14/34

CPC分类号： C23C14/046 ,  C23C14/3407 ,  C23C14/345 ,  C23C14/3492 ,  C23C14/35 ,  H01J37/32596 ,  H01J37/3405 ,  H01L21/2855 ,  H01L21/32131 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76868

摘要： Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.

摘要翻译： 公开了用于在半导体晶片的通路和沟槽中实现蚀刻和/或沉积选择性的装置和方法实施例。 也就是说，半导体晶片的每个通孔的底部的沉积覆盖不同于这种晶片的每个沟槽的底部的覆盖。 选择性可以被配置为导致每个通孔中的穿孔而不损坏每个沟槽等的底部处的电介质材料。 在这种配置中，沉积在每个沟槽中的覆盖率大于沉积在每个通孔中的覆盖量。

公开(公告)号：US06541371B1

公开(公告)日：2003-04-01

申请号：US09491853

申请日：2000-01-26

申请人： Kaihan A. Ashtiani ,  Maximilian A. Biberger ,  Erich R. Klawuhn ,  Kwok Fai Lai ,  Karl B. Levy ,  J. Patrick Rymer

发明人： Kaihan A. Ashtiani ,  Maximilian A. Biberger ,  Erich R. Klawuhn ,  Kwok Fai Lai ,  Karl B. Levy ,  J. Patrick Rymer

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76873 ,  H01L21/76876

摘要： A method of depositing thin films comprising tantalum, tantalum nitride, and copper for barrier films and seed layers within high aspect ratio openings used for copper interconnects. The barrier films and seed layers are deposited at extremely low temperature conditions wherein the wafer stage temperature of the sputter source is chilled to about −70° C. to about 0° C. Most preferably, the present invention is practiced using a hollow cathode magnetron. The resulting tantalum and/or tantalum nitride barrier films and copper seed layers are superior in surface smoothness, grain size and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.

摘要翻译： 一种用于在用于铜互连的高纵横比开口中沉积用于阻挡膜和种子层的钽，氮化钽和铜的薄膜的方法。 阻挡膜和种子层在极低温度条件下沉积，其中溅射源的晶片台温度被冷却至约-70℃至约0℃。最优选地，本发明使用空心阴极磁控管 。 所得到的钽和/或氮化钽阻挡膜和铜籽晶层的表面平滑度，晶粒尺寸和均匀性都是优异的，使得高纵横比开口的后续填充基本上无空隙。

公开(公告)号：US07510634B1

公开(公告)日：2009-03-31

申请号：US11558693

申请日：2006-11-10

申请人： Erich R. Klawuhn ,  Robert Rozbicki ,  Girish A. Dixit

发明人： Erich R. Klawuhn ,  Robert Rozbicki ,  Girish A. Dixit

IPC分类号： C23C14/35

CPC分类号： C23C14/046 ,  C23C14/3407 ,  C23C14/345 ,  C23C14/3492 ,  C23C14/35 ,  H01J37/32596 ,  H01J37/3405 ,  H01L21/2855 ,  H01L21/32131 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76868

摘要： Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.

摘要翻译： 公开了用于在半导体晶片的通路和沟槽中实现蚀刻和/或沉积选择性的装置和方法实施例。 也就是说，半导体晶片的每个通孔的底部的沉积覆盖不同于这种晶片的每个沟槽的底部的覆盖。 选择性可以被配置为导致每个通孔中的穿孔而不损坏每个沟槽等的底部处的电介质材料。 在这种配置中，沉积在每个沟槽中的覆盖率大于沉积在每个通孔中的覆盖量。