公开(公告)号：US06784367B2

公开(公告)日：2004-08-31

申请号：US10374449

申请日：2003-02-25

申请人： Ernest J. Russell ,  Bharath Nagabhushanam ,  Terry Lee ,  Roger Norwood

发明人： Ernest J. Russell ,  Bharath Nagabhushanam ,  Terry Lee ,  Roger Norwood

IPC分类号： H01L2302

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

摘要： Microelectronic devices having a protected input and methods for manufacturing such microelectronic devices. A microelectronic device has a microelectronic die and a support structure for coupling the die to voltage and signal sources. The microelectronic die can have integrated circuitry and a plurality of bond-pads coupled to the integrated circuitry. The bond-pads, for example, can include a reference voltage (Vref) bond-pad and a signal bond-pad adjacent to the Vref bond-pad. The signal bond-pad can be for a clock signal, a data signal, a strobe signal, an address signal, or another type signal for operating the integrated circuitry. The support structure can be a lead frame or a interposing substrate having a plurality of conductive members coupled to the bond-pads of the die. The conductive members can accordingly be metal pins in the case of lead frames or traces and solder ball-pads in the case of interposing substrates. Each conductive member can have a first end with a bond-site proximate to a corresponding bond-pad of the die, a second end defining an external connector, and an elongated conductive section connecting the bond-site to the external connector. The conductive members are generally arranged so that at least some of the bond-sites are arranged in a first row in which the bond-sites and a portion of the elongated sections are spaced apart from one other by a first gap width. The support structure can more specifically include a first conductive member having a first bond-site coupled to the Vref bond-pad by a first wire-bond line and a second conductive member having a second bond-site coupled to the signal bond-pad by a second wire-bond line. The first bond-site of the first conductive member can be spaced apart from the second bond-site of the second conductive member by a second gap width greater than the first gap width.

公开(公告)号：US06548757B1

公开(公告)日：2003-04-15

申请号：US09649765

申请日：2000-08-28

申请人： Ernest J. Russell ,  Bharath Nagabhushanam ,  Terry Lee ,  Roger Norwood

发明人： Ernest J. Russell ,  Bharath Nagabhushanam ,  Terry Lee ,  Roger Norwood

IPC分类号： H01L2302

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

摘要： Microelectronic devices having a protected input and methods for manufacturing such microelectronic devices. A microelectronic device has a microelectronic die and a support structure for coupling the die to voltage and signal sources. The microelectronic die can have integrated circuitry and a plurality of bond-pads coupled to the integrated circuitry. The bond-pads, for example, can include a reference voltage (Vref) bond-pad and a signal bond-pad adjacent to the Vref bond-pad. The signal bond-pad can be for a clock signal, a data signal, a strobe signal, an address signal, or another type signal for operating the integrated circuitry. The support structure can be a lead frame or a interposing substrate having a plurality of conductive members coupled to the bond-pads of the die. The conductive members can accordingly be metal pins in the case of lead frames or traces and solder ball-pads in the case of interposing substrates. Each conductive member can have a first end with a bond-site proximate to a corresponding bond-pad of the die, a second end defining an external connector, and an elongated conductive section connecting the bond-site to the external connector. The conductive members are generally arranged so that at least some of the bond-sites are arranged in a first row in which the bond-sites and a portion of the elongated sections are spaced apart from one other by a first gap width. The support structure can more specifically include a first conductive member having a first bond-site coupled to the Vref bond-pad by a first wire-bond line and a second conductive member having a second bond-site coupled to the signal bond-pad by a second wire-bond line. The first bond-site of the first conductive member can be spaced apart from the second bond-site of the second conductive member by a second gap width greater than the first gap width.

公开(公告)号：US6069829A

公开(公告)日：2000-05-30

申请号：US408093

申请日：1999-09-27

申请人： Yutaka Komai ,  Roger Norwood ,  Daniel B. Penny

发明人： Yutaka Komai ,  Roger Norwood ,  Daniel B. Penny

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/20 ,  G11C29/34 ,  G11C29/40

CPC分类号： G11C29/14 ,  G11C29/12015 ,  G11C29/20 ,  G11C29/40 ,  G11C2029/3602

摘要： A circuit is designed with a clock circuit (215, 217) coupled to receive a control signal having a first logic state and a second logic state. The clock circuit produces a first clock signal (CLK) response to the first logic state and a second clock signal (*CLK) in response to the second logic state. The second clock signal has a frequency at least twice a frequency of the first clock signal. An address counter (221) is coupled to receive one of the first and second clock signals. The address counter produces a sequence of address signals corresponding to the one of the first and second clock signals. An array of memory cells is arranged to produce a sequence of data bits corresponding to the sequence of address signals. A logic circuit (235, 239, 240) is coupled to receive the sequence of data bits. The logic circuit produces a logical combination of the sequence of data bits.

摘要翻译： 电路被设计成具有耦合以接收具有第一逻辑状态和第二逻辑状态的控制信号的时钟电路（215,217）。 时钟电路响应于第二逻辑状态产生响应于第一逻辑状态的第一时钟信号（CLK）和第二时钟信号（* CLK）。 第二时钟信号的频率至少是第一时钟信号频率的两倍。 地址计数器（221）被耦合以接收第一和第二时钟信号中的一个。 地址计数器产生对应于第一和第二时钟信号之一的地址信号序列。 存储器单元的阵列被布置成产生与地址信号序列相对应的数据位序列。 逻辑电路（235,239,240）被耦合以接收数据位序列。 逻辑电路产生数据位序列的逻辑组合。