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    Shallow trench isolation method for shielding trapped charge in a semiconductor device
    1.
    发明授权
    Shallow trench isolation method for shielding trapped charge in a semiconductor device 失效
    用于屏蔽半导体器件中的俘获电荷的浅沟槽隔离方法

    公开(公告)号：US07385275B2

    公开(公告)日：2008-06-10

    申请号：US11276132

    申请日：2006-02-15

    申请人： Ethan Harrison Cannon ,  Shunhua Thomas Chang ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III

    发明人： Ethan Harrison Cannon ,  Shunhua Thomas Chang ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III

    IPC分类号： H01L29/00 ,  H01L21/762 ,  H01L21/763

    CPC分类号： H01L21/76224 ,  H01L29/7833

    摘要： A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.

    摘要翻译： 一种用于形成半导体结构的半导体结构和相关方法。 半导体结构包括第一场效应晶体管（FET），第二FET和浅沟槽隔离（STI）结构。 第一FET包括由硅衬底的一部分形成的沟道区，在沟道区上形成的栅极电介质和包括与栅极电介质直接物理接触的底表面的栅电极。 沟道区的顶表面位于第一平面内，栅电极的底表面位于第二平面内。 STI结构包括导电STI填充结构。 导电STI填充结构的顶表面在第一平面上方高于第一距离D 1，并且在第二平面上方高于第二平面的第二距离D 2 2 < D 1 。

    High performance single event upset hardened SRAM cell
    4.
    发明授权
    High performance single event upset hardened SRAM cell 有权
    高性能单事件硬化SRAM单元

    公开(公告)号：US07397692B1

    公开(公告)日：2008-07-08

    申请号：US11612809

    申请日：2006-12-19

    申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack A. Mandelman

    发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack A. Mandelman

    IPC分类号： G11C11/00

    CPC分类号： G11C11/4125

    摘要： An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.

    摘要翻译： 一个SRAM单元。 SRAM单元包括第一CMOS反相器和第二CMOS反相器，连接到第二反相器的输出的第一反相器的输入和连接到第一反相器的输出的第二反相器的输入， 第一CMOS反相器的输出和第一电容器的第一板，第一电容器的第二板连接到电源的高电压端子; 插入在所述第二CMOS反相器的输出端和第二电容器的第一板之间的第二MOSFET，所述第二电容器的第二板连接到所述电源的高电压端子; 以及连接到第一MOSFET的栅极和第二MOSFET的栅极的控制信号线。

    Method of fabricating semiconductor structures for latch-up suppression
    5.
    发明授权
    Method of fabricating semiconductor structures for latch-up suppression 失效
    制造用于闭锁抑制的半导体结构的方法

    公开(公告)号：US07648869B2

    公开(公告)日：2010-01-19

    申请号：US11330689

    申请日：2006-01-12

    申请人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/0921 ,  H01L21/823878

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁相邻的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。

    Well isolation trenches (WIT) for CMOS devices
    7.
    发明授权
    Well isolation trenches (WIT) for CMOS devices 失效
    用于CMOS器件的隔离沟槽（WIT）

    公开(公告)号：US07737504B2

    公开(公告)日：2010-06-15

    申请号：US11759981

    申请日：2007-06-08

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L29/772

    CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

    摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

    摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

    LAYER PATTERNING USING DOUBLE EXPOSURE PROCESSES IN A SINGLE PHOTORESIST LAYER
    10.
    发明申请
    LAYER PATTERNING USING DOUBLE EXPOSURE PROCESSES IN A SINGLE PHOTORESIST LAYER 有权
    在单个光电层中使用双重曝光过程的层状图

    公开(公告)号：US20090035708A1

    公开(公告)日：2009-02-05

    申请号：US11831099

    申请日：2007-07-31

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

    IPC分类号： G03F7/20

    CPC分类号： G03F7/2024 ,  G03F7/38 ,  G03F7/40 ,  G03F7/70425

    摘要： A structure and a method for forming the same. The method includes providing a structure which includes (a) a to-be-patterned layer, (b) a photoresist layer on top of the to-be-patterned layer wherein the photoresist layer includes a first opening, and (c) a cap region on side walls of the first opening. A first top surface of the to-be-patterned layer is exposed to a surrounding ambient through the first opening. The method further includes performing a first lithography process resulting in a second opening in the photoresist layer. The second opening is different from the first opening. A second top surface of the to-be-patterned layer is exposed to a surrounding ambient through the second opening.

    摘要翻译： 一种结构及其形成方法。 该方法包括提供一种结构，其包括（a）待图案化层，（b）在待图案化层的顶部上的光致抗蚀剂层，其中光致抗蚀剂层包括第一开口，和（c）帽 区域在第一开口的侧壁上。 待图案化层的第一顶表面通过第一开口暴露于周围环境。 该方法还包括执行在光致抗蚀剂层中产生第二开口的第一光刻工艺。 第二个开口与第一个开口不同。 待图案化层的第二顶表面通过第二开口暴露于周围环境。