公开(公告)号：US07385275B2

公开(公告)日：2008-06-10

申请号：US11276132

申请日：2006-02-15

申请人： Ethan Harrison Cannon ,  Shunhua Thomas Chang ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III

发明人： Ethan Harrison Cannon ,  Shunhua Thomas Chang ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III

IPC分类号： H01L29/00 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/76224 ,  H01L29/7833

摘要： A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.

摘要翻译： 一种用于形成半导体结构的半导体结构和相关方法。 半导体结构包括第一场效应晶体管（FET），第二FET和浅沟槽隔离（STI）结构。 第一FET包括由硅衬底的一部分形成的沟道区，在沟道区上形成的栅极电介质和包括与栅极电介质直接物理接触的底表面的栅电极。 沟道区的顶表面位于第一平面内，栅电极的底表面位于第二平面内。 STI结构包括导电STI填充结构。 导电STI填充结构的顶表面在第一平面上方高于第一距离D 1，并且在第二平面上方高于第二平面的第二距离D 2 2 < D 1 。

公开(公告)号：US07648869B2

公开(公告)日：2010-01-19

申请号：US11330689

申请日：2006-01-12

申请人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L21/8238

CPC分类号： H01L27/0921 ,  H01L21/823878

摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁相邻的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。

公开(公告)号：US08614489B2

公开(公告)日：2013-12-24

申请号：US13614072

申请日：2012-09-13

申请人： John B. Campi ,  Shunhua Thomas Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

发明人： John B. Campi ,  Shunhua Thomas Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC分类号： H01L29/76

CPC分类号： H01L29/74 ,  H01L21/823892 ,  H01L27/0262 ,  H01L27/0928 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

摘要翻译： 使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。 垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。 也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。