公开(公告)号：US6002181A

公开(公告)日：1999-12-14

申请号：US551917

申请日：1995-10-23

申请人： Etsuo Yamada ,  Yasushi Shiraishi ,  Hiroshi Kawano ,  Shinji Ohuchi ,  Hidekazu Nasu

发明人： Etsuo Yamada ,  Yasushi Shiraishi ,  Hiroshi Kawano ,  Shinji Ohuchi ,  Hidekazu Nasu

IPC分类号： H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L23/28

CPC分类号： H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/4951 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/8592 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165

摘要： A resin molded type semiconductor device has an inner portion sandwiched between two outer surfaces. The device includes a chip support with a first, inwardly facing surface and a second, outwardly facing surface. The device also includes a semiconductor element with a first, inwardly facing surface and a second, outwardly facing surface. The respective first surfaces of the chip support and semiconductor element are fixed to each other. A mold resin is provided to seal the entire semiconductor device except for the respective second surfaces of the chip support and semiconductor element which remain exposed as part of the two outer surfaces of the device, in order to keep the semiconductor device thin.

摘要翻译： 树脂模制型半导体器件具有夹在两个外表面之间的内部部分。 该装置包括具有第一面向内的表面和第二向外表面的芯片支撑件。 该装置还包括具有第一面向内的表面和第二向外表面的半导体元件。 芯片支撑体和半导体元件的各个第一表面彼此固定。 为了保持半导体器件的薄型化，提供了一种模制树脂来密封整个半导体器件，除了作为器件的两个外表面的一部分而保持暴露的芯片支撑件和半导体元件的相应的第二表面之外。

公开(公告)号：US09070482B2

公开(公告)日：2015-06-30

申请号：US13159517

申请日：2011-06-14

申请人： Satoshi Miyazaki ,  Hidekazu Nasu

发明人： Satoshi Miyazaki ,  Hidekazu Nasu

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C29/00

CPC分类号： G11C29/70 ,  G11C29/76 ,  H01L2224/48147

摘要： An MCP type semiconductor memory device having a defective cell remedy function, enables easy design and manufacture while minimizing chip area increase. The semiconductor memory device includes memory chips and a memory controller chip that designates an address of a memory chip according to an access request received from outside and controls access to the designated address. Each memory chip includes first and second storage regions and an information holder that holds address information representing associations between addresses in the first and second storage regions. The memory controller chip includes an address translating part that performs, upon receiving a request to access a specific address in the first storage region indicated by the address information, address designation by translating the specific address in the first storage region to an address in the second storage region corresponding to the specific address based on the associations represented by the address information.

摘要翻译： 具有缺陷电池补救功能的MCP型半导体存储器件能够容易地进行设计和制造，同时最小化芯片面积增加。 半导体存储器件包括存储器芯片和存储器控制器芯片，其根据从外部接收的访问请求来指定存储器芯片的地址，并控制对指定地址的访问。 每个存储器芯片包括第一和第二存储区域以及信息保持器，其保存表示第一和第二存储区域中的地址之间的关联的地址信息。 存储器控制器芯片包括：地址转换部，其在接收到由地址信息指示的第一存储区域中访问特定地址的请求时，通过将第一存储区域中的特定地址转换为第二存储区域中的地址来执行地址指定 存储区域基于由地址信息表示的关联而与特定地址相对应。

公开(公告)号：US08723303B2

公开(公告)日：2014-05-13

申请号：US13159513

申请日：2011-06-14

申请人： Hidekazu Nasu ,  Satoshi Miyazaki

发明人： Hidekazu Nasu ,  Satoshi Miyazaki

IPC分类号： H01L23/02 ,  H01L23/48

CPC分类号： G11C5/02 ,  H01L25/0652 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2225/06562 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip adjacent the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip.

摘要翻译： 一种MCP型半导体存储器件，其结构是将包括多个堆叠的存储器芯片的堆叠存储器芯片和存储器控制器芯片并置在基板上，这实现了封装尺寸的减小。 半导体存储器件包括堆叠存储器芯片，其包括多个层叠的存储器芯片，其上提供有堆叠存储器芯片的衬底以及与衬底上的堆叠存储器芯片相邻的存储器控​​制器芯片。 堆叠存储器芯片被构造成使得上部存储器芯片被堆叠以便相对于位于上部存储器芯片正下方的存储器芯片朝向存储器控制器芯片的安装位置移动。 存储器控制器芯片的至少一部分被接收在衬底和向存储器控制器芯片突出的堆叠存储器芯片的一部分之间的空间内。

公开(公告)号：US20110314234A1

公开(公告)日：2011-12-22

申请号：US13159517

申请日：2011-06-14

申请人： Satoshi Miyazaki ,  Hidekazu Nasu

发明人： Satoshi Miyazaki ,  Hidekazu Nasu

IPC分类号： G06F12/00

CPC分类号： G11C29/70 ,  G11C29/76 ,  H01L2224/48147

摘要： An MCP type semiconductor memory device having a defective cell remedy function, which enables easy design and manufacture while minimizing chip area increase, is provided. The semiconductor memory device includes memory chips and a memory controller chip that designates an address of a memory chip according to an access request received from outside and controls access to the designated address. Each memory chip includes first and second storage regions and an information holder that holds address information representing associations between addresses in the first and second storage regions. The memory controller chip includes an address translating part that performs, upon receiving a request to access a specific address in the first storage region indicated by the address information, address designation by translating the specific address in the first storage region to an address in the second storage region corresponding to the specific address based on the associations represented by the address information.

摘要翻译： 提供具有缺陷电池补救功能的MCP型半导体存储器件，其能够在最小化芯片面积增加的同时实现容易的设计和制造。 半导体存储器件包括存储器芯片和存储器控制器芯片，其根据从外部接收的访问请求来指定存储器芯片的地址，并控制对指定地址的访问。 每个存储器芯片包括第一和第二存储区域以及信息保持器，其保存表示第一和第二存储区域中的地址之间的关联的地址信息。 存储器控制器芯片包括：地址转换部，其在接收到由地址信息指示的第一存储区域中访问特定地址的请求时，通过将第一存储区域中的特定地址转换为第二存储区域中的地址来执行地址指定 存储区域基于由地址信息表示的关联而与特定地址相对应。

公开(公告)号：US20110309525A1

公开(公告)日：2011-12-22

申请号：US13159513

申请日：2011-06-14

申请人： Hidekazu Nasu ,  Satoshi Miyazaki

发明人： Hidekazu Nasu ,  Satoshi Miyazaki

IPC分类号： H01L23/538

CPC分类号： G11C5/02 ,  H01L25/0652 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2225/06562 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate is provided, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip provided adjacent to the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip.

摘要翻译： 提供一种MCP型半导体存储器件，其具有将包括多个堆叠的存储器芯片的堆叠存储器芯片和存储器控制器芯片并置在基板上的结构，这实现了封装尺寸的减小。 半导体存储器件包括堆叠存储器芯片，其包括多个层叠的存储器芯片，其上提供有堆叠存储器芯片的衬底以及与衬底上的堆叠存储器芯片相邻设置的存储器控​​制器芯片。 堆叠存储器芯片被构造成使得上部存储器芯片被堆叠以便相对于位于上部存储器芯片正下方的存储器芯片朝向存储器控制器芯片的安装位置移动。 存储器控制器芯片的至少一部分被接收在衬底和向存储器控制器芯片突出的堆叠存储器芯片的一部分之间的空间内。