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    Method of forming a metal layer and a method of fabricating a semiconductor device
    1.
    发明授权
    Method of forming a metal layer and a method of fabricating a semiconductor device 有权
    形成金属层的方法和制造半导体器件的方法

    公开(公告)号：US08119526B2

    公开(公告)日：2012-02-21

    申请号：US12955093

    申请日：2010-11-29

    申请人： Eun-ji Jung ,  Woong-hee Sohn ,  Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-hee Kim

    发明人： Eun-ji Jung ,  Woong-hee Sohn ,  Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-hee Kim

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76849 ,  H01L21/28562

    摘要： A method of forming metal films includes preparing a substrate, on which an insulating layer and a metal layer formed of a first metal are exposed; and forming a metal capping layer by supplying an organic precursor of a second metal onto the substrate to deposit the second metal simultaneously on the insulating layer and the metal layer, wherein the second metal capping layer has different thicknesses on the insulating layer and the metal layer.

    摘要翻译： 一种形成金属膜的方法包括制备其上露出由第一金属形成的绝缘层和金属层的基板; 以及通过将第二金属的有机前体供给到所述基板上以同时在所述绝缘层和所述金属层上沉积所述第二金属而形成金属覆盖层，其中所述第二金属覆盖层在所述绝缘层和所述金属层上具有不同的厚度 。

    Methods of Forming Integrated Circuit Devices Having Stacked Gate Electrodes
    9.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Stacked Gate Electrodes 有权
    形成具有堆叠栅电极的集成电路器件的方法

    公开(公告)号：US20090325371A1

    公开(公告)日：2009-12-31

    申请号：US12424922

    申请日：2009-04-16

    申请人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

    发明人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/66545

    摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

    摘要翻译： 提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层 栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

    Method of fabricating semiconductor device
    10.
    发明申请
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20100112772A1

    公开(公告)日：2010-05-06

    申请号：US12460945

    申请日：2009-07-27

    申请人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

    发明人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11573 ,  H01L21/28123 ,  H01L21/28282

    摘要： A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.

    摘要翻译： 一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。