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    METHOD OF FILLING A TRENCH AND METHOD OF FORMING AN ISOLATING LAYER STRUCTURE USING THE SAME
    1.
    发明申请
    METHOD OF FILLING A TRENCH AND METHOD OF FORMING AN ISOLATING LAYER STRUCTURE USING THE SAME 有权
    填充TRENCH的方法和使用其形成隔离层结构的方法

    公开(公告)号：US20090191687A1

    公开(公告)日：2009-07-30

    申请号：US12339125

    申请日：2008-12-19

    申请人： Eunkee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Young-Sun Kim

    发明人： Eunkee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Young-Sun Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76237 ,  H01L21/76232

    摘要： A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

    摘要翻译： 在衬底中填充沟槽的方法确保在占据沟槽的材料中不留下空隙或接缝。 首先，形成预备绝缘层，以沿着沟槽的底部和侧面并且沿衬底的上表面连续延伸。 然后将杂质注入到与第一沟槽的顶部相邻的初级绝缘层的一部分中，以形成具有掺杂区域和未掺杂区域的第一绝缘层。 去除掺杂区域以在第一沟槽的底部和侧面形成第一绝缘层图案，并且该第一绝缘层图案限定第二沟槽。 然后用绝缘材料填充第二沟槽。

    Method of filling a trench and method of forming an isolating layer structure using the same
    2.
    发明授权
    Method of filling a trench and method of forming an isolating layer structure using the same 有权
    填充沟槽的方法和使用其形成隔离层结构的方法

    公开(公告)号：US07858492B2

    公开(公告)日：2010-12-28

    申请号：US12339125

    申请日：2008-12-19

    申请人： Eunkee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Young-Sun Kim

    发明人： Eunkee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Young-Sun Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76237 ,  H01L21/76232

    摘要： A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

    摘要翻译： 在衬底中填充沟槽的方法确保在占据沟槽的材料中不留下空隙或接缝。 首先，形成预备绝缘层，以沿着沟槽的底部和侧面并且沿衬底的上表面连续延伸。 然后将杂质注入到与第一沟槽的顶部相邻的初级绝缘层的一部分中，以形成具有掺杂区域和未掺杂区域的第一绝缘层。 去除掺杂区域以在第一沟槽的底部和侧面形成第一绝缘层图案，并且该第一绝缘层图案限定第二沟槽。 然后用绝缘材料填充第二沟槽。

    Semiconductor device having trench isolation region and methods of fabricating the same
    3.
    发明授权
    Semiconductor device having trench isolation region and methods of fabricating the same 有权
    具有沟槽隔离区域的半导体器件及其制造方法

    公开(公告)号：US07781304B2

    公开(公告)日：2010-08-24

    申请号：US12216820

    申请日：2008-07-11

    申请人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    发明人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229

    摘要： A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively.

    摘要翻译： 提供了具有沟槽隔离区域的半导体器件及其制造方法。 该方法包括在衬底中形成第一沟槽区域和在衬底中具有比第一沟槽区域宽的宽度的第二沟槽区域。 下部材料层可以填充第一和第二沟槽区域。 可以通过第一蚀刻工艺蚀刻下部材料层，以形成残留在第一沟槽区域中的第一初步下部材料层图案，并形成保留在第二沟槽区域中的第二预备下部材料层图案。 第二初步下层材料层图案的上表面可以处于与第一预备下层材料层图案不同的高度。 可以通过第二蚀刻工艺蚀刻第一和第二初级下部材料层图案，以形成具有基本上相同高度的顶表面的第一和第二下部材料层图案。 可以分别在第一和第二下部材料层图案上形成第一和第二上部材料层图案。

    Semiconductor devices having trench isolation regions and methods of manufacturing semiconductor devices having trench isolation regions
    4.
    发明申请
    Semiconductor devices having trench isolation regions and methods of manufacturing semiconductor devices having trench isolation regions 审中-公开
    具有沟槽隔离区域的半导体器件和制造具有沟槽隔离区域的半导体器件的方法

    公开(公告)号：US20090045483A1

    公开(公告)日：2009-02-19

    申请号：US12222630

    申请日：2008-08-13

    申请人： Sang-Ho Rha ,  Eun-Kee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek

    发明人： Sang-Ho Rha ,  Eun-Kee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek

    IPC分类号： H01L21/762 ,  H01L23/58

    CPC分类号： H01L21/76232

    摘要： A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region.

    摘要翻译： 半导体器件可以包括半导体衬底，沟槽区，缓冲图案，间隙填充层和晶体管。 沟槽区域可以设置在半导体衬底中以限定有源区域。 缓冲图案和间隙填充层可以设置在沟槽区域中。 缓冲图案和间隙填充层可以填充沟槽区域。 间隙填充层可以由缓冲图案致密化。 晶体管可以设置在有源区中。 半导体器件的制造方法可以包括：在半导体衬底中形成沟槽区域; 在所述第一沟槽区的内壁上形成缓冲层; 形成间隙填充层，填充沟槽区域; 进行热处理以使杂质与氧反应，形成缓冲图案; 以及在有源区中形成晶体管。

    Semiconductor device having trench isolation region and methods of fabricating the same
    5.
    发明申请
    Semiconductor device having trench isolation region and methods of fabricating the same 有权
    具有沟槽隔离区域的半导体器件及其制造方法

    公开(公告)号：US20090020847A1

    公开(公告)日：2009-01-22

    申请号：US12216820

    申请日：2008-07-11

    申请人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    发明人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    IPC分类号： H01L21/762 ,  H01L23/58

    CPC分类号： H01L21/76229

    摘要： A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively.

    摘要翻译： 提供了具有沟槽隔离区域的半导体器件及其制造方法。 该方法包括在衬底中形成第一沟槽区域和在衬底中具有比第一沟槽区域宽的宽度的第二沟槽区域。 下部材料层可以填充第一和第二沟槽区域。 可以通过第一蚀刻工艺蚀刻下部材料层，以形成残留在第一沟槽区域中的第一初步下部材料层图案，并形成保留在第二沟槽区域中的第二预备下部材料层图案。 第二初步下层材料层图案的上表面可以处于与第一预备下层材料层图案不同的高度。 可以通过第二蚀刻工艺蚀刻第一和第二初级下部材料层图案，以形成具有基本上相同高度的顶表面的第一和第二下部材料层图案。 可以分别在第一和第二下部材料层图案上形成第一和第二上部材料层图案。

    Semiconductor device isolation structures and methods of fabricating such structures
    6.
    发明授权
    Semiconductor device isolation structures and methods of fabricating such structures 有权
    半导体器件隔离结构及其制造方法

    公开(公告)号：US07674685B2

    公开(公告)日：2010-03-09

    申请号：US11654588

    申请日：2007-01-18

    申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

    摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

    摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

    Semiconductor device isolation structures and methods of fabricating such structures
    8.
    发明申请
    Semiconductor device isolation structures and methods of fabricating such structures 有权
    半导体器件隔离结构及其制造方法

    公开(公告)号：US20080014711A1

    公开(公告)日：2008-01-17

    申请号：US11654588

    申请日：2007-01-18

    申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

    摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

    摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。