公开(公告)号：US20110204872A1

公开(公告)日：2011-08-25

申请号：US12922665

申请日：2009-03-09

申请人： Evelyne Gridelet ,  Almudena Huerta ,  Pierre Goarin ,  Jan Sonsky

发明人： Evelyne Gridelet ,  Almudena Huerta ,  Pierre Goarin ,  Jan Sonsky

IPC分类号： G01N27/00 ,  H01L29/66 ,  H01L31/118

CPC分类号： H01L29/7391 ,  G01N27/4145

摘要： A sensor device (100, 2800) for detecting particles, the sensor device (100, 2800) comprising a substrate (102), a first doped region (104) formed in the substrate (102) by a first dopant of a first type of conductivity, a second doped region (106, 150) formed in the substrate (102) by a second dopant of a second type of conductivity which differs from the first type of conductivity, a depletion region (108) at a junction between the first doped region (104) and the second doped region (106, 150), a sensor active region (110) adapted to influence a property of the depletion region (108) in the presence of the particles, and a detection unit (112) adapted to detect the particles based on an electric measurement performed upon application of a predetermined reference voltage between the first doped region (104) and the second doped region (106, 150), the electric measurement being indicative of the presence of the particles in the sensor active region (110).

摘要翻译： 一种用于检测颗粒的传感器装置（100,2800），所述传感器装置（100,2800）包括衬底（102），通过第一类型的第一掺杂剂在衬底（102）中形成的第一掺杂区（104） 通过与第一类型的导电性不同的第二导电类型的第二掺杂剂形成在衬底（102）中的第二掺杂区（106,150），第一掺杂区 区域（104）和第二掺杂区域（106,150），适于在存在颗粒的情况下影响耗尽区（108）的性质的传感器有源区（110），以及适于 基于在第一掺杂区域（104）和第二掺杂区域（106,150）之间施加预定参考电压进行的电测量来检测颗粒，电测量表示传感器中存在颗粒活性 区域（110）。

公开(公告)号：US09799757B2

公开(公告)日：2017-10-24

申请号：US12922665

申请日：2009-03-09

申请人： Evelyne Gridelet ,  Almudena Huerta ,  Pierre Goarin ,  Jan Sonsky

发明人： Evelyne Gridelet ,  Almudena Huerta ,  Pierre Goarin ,  Jan Sonsky

IPC分类号： G01N27/00 ,  H01L29/739 ,  G01N27/414

CPC分类号： H01L29/7391 ,  G01N27/4145

摘要： A sensor device (100, 2800) for detecting particles, the sensor device (100, 2800) comprising a substrate (102), a first doped region (104) formed in the substrate (102) by a first dopant of a first type of conductivity, a second doped region (106, 150) formed in the substrate (102) by a second dopant of a second type of conductivity which differs from the first type of conductivity, a depletion region (108) at a junction between the first doped region (104) and the second doped region (106, 150), a sensor active region (110) adapted to influence a property of the depletion region (108) in the presence of the particles, and a detection unit (112) adapted to detect the particles based on an electric measurement performed upon application of a predetermined reference voltage between the first doped region (104) and the second doped region (106, 150), the electric measurement being indicative of the presence of the particles in the sensor active region (110).

公开(公告)号：US20080203462A1

公开(公告)日：2008-08-28

申请号：US12067992

申请日：2006-09-26

申请人： Pierre Goarin

发明人： Pierre Goarin

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory device on a substrate layer (2) comprises source and drain regions (3) and a channel region (4). The source and drain regions (3) and the channel region (4) are arranged in a semiconductor layer (20) on the substrate layer (2). The channel region (4) is fin-shaped and extends longitudinally (X) between the source region and the drain region (3). The channel region (4) comprises two fin portions (4a, 4b) and an intra-fin space (10), the fin portions (4a, 4b) extending in the longitudinal direction (X) and being spaced apart, and the intra-fin space (10) being located in between the fin portions (4a, 4b), and a charge storage area (11, 12; 15, 12) is located in the intra-fin space (10) between the fin portions (4a, 4b).

摘要翻译： 衬底层（2）上的非易失性存储器件包括源极和漏极区（3）和沟道区（4）。 源极和漏极区域（3）和沟道区域（4）被布置在衬底层（2）上的半导体层（20）中。 沟道区域（4）是鳍状的并且在源极区域和漏极区域（3）之间纵向延伸（X）。 通道区域（4）包括两个翅片部分（4a，4b）和翅片内空间（10），翅片部分（4a，4b）沿纵向方向（X）延伸并间隔开， 并且所述翅片内空间（10）位于所述翅片部分（4a，4b）之间，并且电荷存储区域（11,12; 15,12）位于所述翅片内空间（10）中 翅片部分（4a，4b）。

公开(公告)号：US08350308B2

公开(公告)日：2013-01-08

申请号：US12920747

申请日：2009-03-05

申请人： Aurelie Humbert ,  Pierre Goarin ,  Romain Delhougne

发明人： Aurelie Humbert ,  Pierre Goarin ,  Romain Delhougne

IPC分类号： H01L27/108

CPC分类号： H01L23/573 ,  H01L23/5223 ,  H01L27/112 ,  H01L27/11213 ,  H01L27/11253 ,  H01L2924/0002 ,  H01L2924/00

摘要： A read only memory is manufactured with a plurality of transistors (4) on a semiconductor substrate (2). A low-k dielectric (10) and interconnects (14) are provided over the transistors (4). To program the read only memory, the low-k dielectric is implanted with ions (22) in unmasked regions (20) leaving the dielectric unimplanted in masked regions (18). The memory thus formed is difficult to reverse engineer.

摘要翻译： 在半导体衬底（2）上制造具有多个晶体管（4）的只读存储器。 在晶体管（4）之上提供低k电介质（10）和互连（14）。 为了对只读存储器进行编程，在未掩模区域（20）中注入低k电介质，离子（22）留下未被掩盖在掩蔽区域（18）中的电介质。 这样形成的记忆难以逆向工程。

公开(公告)号：US08110455B2

公开(公告)日：2012-02-07

申请号：US12864775

申请日：2009-01-26

申请人： Pierre Goarin

发明人： Pierre Goarin

IPC分类号： H01L21/00

CPC分类号： H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/78

摘要： A method of manufacturing a semiconductor device (1200), the method comprising forming a sacrificial pattern having a recess on a substrate (402), filling the recess and covering the substrate and the sacrificial pattern with a semiconductor structure, forming an annular trench in the semiconductor structure to expose a portion of the sacrificial pattern and to separate material (904) of the semiconductor structure enclosed by the annular trench from material (906) of the semiconductor structure surrounding the annular trench, removing the exposed sacrificial pattern to expose material of the semiconductor structure filling the recess, and converting the exposed material of the semiconductor structure filling the recess into electrically insulting material (1202).

摘要翻译： 一种制造半导体器件（1200）的方法，所述方法包括在衬底（402）上形成具有凹陷的牺牲图案，填充所述凹部并用半导体结构覆盖所述衬底和所述牺牲图案，在所述衬底 半导体结构以暴露所述牺牲图案的一部分并且将由所述环形沟槽包围的所述半导体结构的材料（904）与围绕所述环形沟槽的所述半导体结构的材料（906）分离，去除所述暴露的牺牲图案以暴露所述牺牲图案的材料 填充凹部的半导体结构，以及将填充凹部的半导体结构的暴露材料转换成电绝缘材料（1202）。

公开(公告)号：US08227857B2

公开(公告)日：2012-07-24

申请号：US12531578

申请日：2008-03-12

申请人： Pierre Goarin

发明人： Pierre Goarin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7825 ,  H01L21/3247 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

摘要： A planar extended drain transistor (100) is provided which comprises a control gate (102), a drain region (109), a channel region (107), and a drift region (108), wherein the drift region (108) is arranged between the channel region (107) and the drain region (109). Furthermore, the control gate (102) is at least partially buried into the channel region (107) and the drift region (108) comprises a doping material density which is lower than the doping material density of the drain region (109).

摘要翻译： 提供了一种平面扩展漏极晶体管（100），其包括控制栅极（102），漏极区域（109），沟道区域（107）和漂移区域（108），其中漂移区域（108）被布置 在沟道区域（107）和漏极区域（109）之间。 此外，控制栅极（102）至少部分地埋入沟道区域（107）中，并且漂移区域（108）包括掺杂材料密度低于漏极区域（109）的掺杂材料密度。

公开(公告)号：US07923363B2

公开(公告)日：2011-04-12

申请号：US11575302

申请日：2005-09-13

申请人： Pierre Goarin ,  Robertus Theodorus Fransiscus Van Schaijk

发明人： Pierre Goarin ,  Robertus Theodorus Fransiscus Van Schaijk

IPC分类号： H01L21/3205

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  Y10S438/954

摘要： Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising: —providing the substrate having the first semiconductor layer; —depositing the charge trapping layer; —depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and —creating a shallow trench isolation in between said at least two non-volatile memory cells.

摘要翻译： 在存储区域中的半导体衬底上制造非易失性存储器件的方法，所述非易失性存储器件包括第一半导体层，电荷俘获层和导电层的电池堆，所述电荷俘获层为 所述第一半导体层和所述导电层之间的中间层，所述电荷俘获层至少包括第一绝缘层; 该方法包括：提供具有第一半导体层的衬底; - 沉积电荷捕获层; - 沉积导电层; 图案化所述单元堆栈以形成至少两个非易失性存储单元，以及在所述至少两个非易失性存储单元之间创建浅沟槽隔离。

公开(公告)号：US20090212347A1

公开(公告)日：2009-08-27

申请号：US11575302

申请日：2005-09-13

申请人： Pierre Goarin ,  Robertus Theodorus Fransiscus Van Schaijk

发明人： Pierre Goarin ,  Robertus Theodorus Fransiscus Van Schaijk

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L21/762

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  Y10S438/954

摘要： Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising:—providing the substrate having the first semiconductor layer;—depositing the charge trapping layer;—depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and—creating a shallow trench isolation in between said at least two non-volatile memory cells.

摘要翻译： 在存储区域中的半导体衬底上制造非易失性存储器件的方法，所述非易失性存储器件包括第一半导体层，电荷俘获层和导电层的电池堆，所述电荷俘获层为 所述第一半导体层和所述导电层之间的中间层，所述电荷俘获层至少包括第一绝缘层; 所述方法包括： - 提供具有所述第一半导体层的所述衬底; - 沉积所述电荷俘获层; - 沉积所述导电层; 图案化所述单元堆叠以形成至少两个非易失性存储单元，以及在所述至少两个非易失性存储单元之间形成浅沟槽隔离。

公开(公告)号：US20080230824A1

公开(公告)日：2008-09-25

申请号：US12067986

申请日：2006-09-26

申请人： Gerben Doornbos ,  Pierre Goarin

发明人： Gerben Doornbos ,  Pierre Goarin

IPC分类号： H01L49/00 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785

摘要： The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.

摘要翻译： 本发明涉及包括半导体源极和漏极区域的衬底层上的非易失性存储器件，半导体沟道区域，电荷存储堆叠和控制栅极; 所述通道区域是翅片状的，具有两个侧壁部分和顶部部分，并且在所述源极区域和所述漏极区域之间延伸; 所述电荷存储堆叠位于所述源极和漏极区域之间并且在所述鳍状通道上延伸，基本上垂直于所述鳍状通道的长度方向; 所述控制栅极与所述电荷存储堆叠接触，其中，接近栅极邻近一个侧壁部分设置并且由中间栅极氧化物层与其隔开，并且所述电荷存储堆叠接触所述另一个侧壁上的所述鳍状沟道 并且通过中间栅极氧化物层与沟道分离。

公开(公告)号：US08063427B2

公开(公告)日：2011-11-22

申请号：US12067992

申请日：2006-09-26

申请人： Pierre Goarin

发明人： Pierre Goarin

IPC分类号： H01L29/788

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory device on a substrate layer (2) comprises source and drain regions (3) and a channel region (4). The source and drain regions (3) and the channel region (4) are arranged in a semiconductor layer (20) on the substrate layer (2). The channel region (4) is fin-shaped and extends longitudinally (X) between the source region and the drain region (3). The channel region (4) comprises two fin portions (4a, 4b) and an intra-fin space (10), the fin portions (4a, 4b) extending in the longitudinal direction (X) and being spaced apart, and the intra-fin space (10) being located in between the fin portions (4a, 4b), and a charge storage area (11, 12; 15, 12) is located in the intra-fin space (10) between the fin portions (4a, 4b).

摘要翻译： 衬底层（2）上的非易失性存储器件包括源极和漏极区（3）和沟道区（4）。 源极和漏极区域（3）和沟道区域（4）被布置在衬底层（2）上的半导体层（20）中。 沟道区域（4）是鳍状的并且在源极区域和漏极区域（3）之间纵向延伸（X）。 通道区域（4）包括两个翅片部分（4a，4b）和翅片内空间（10），翅片部分（4a，4b）沿纵向方向（X）延伸并间隔开， 翅片空间（10）位于翅片部分（4a，4b）之间，并且电荷存储区域（11,12; 15,12）位于翅片部分（4a，4b）之间的翅片内空间（10） 4b）。