公开(公告)号：US20160112312A1

公开(公告)日：2016-04-21

申请号：US14875994

申请日：2015-10-06

申请人： FUJITSU LIMITED

发明人： Shinya HIRAMOTO ,  Tomohiro Inoue ,  Shun Ando ,  Masahiro Maeda ,  Masao Yoshikawa

IPC分类号： H04L12/741 ,  H04L12/861

CPC分类号： H04L45/74 ,  H04L49/9005

摘要： A communication apparatus includes a connection port and a processor. The connection port is connected to a switch apparatus. The processor is configured to acquire data to be transmitted to an external apparatus. The processor is configured to generate a packet destined to the external apparatus. The packet contains the data. The processor is configured to store the packet in a buffer. The processor is configured to acquire the packet from the buffer. The processor is configured to transmit the packet to the switch apparatus via the connection port. The processor is configured to acquire a state of a network to which the connection port is connected. The processor is configured to control, on basis of the state of the network and a predetermined packet generation time, a number of packets to be generated.

摘要翻译： 通信装置包括连接端口和处理器。 连接端口连接到开关装置。 处理器被配置为获取要发送到外部设备的数据。 处理器被配置为生成去往外部设备的分组。 数据包包含数据。 处理器被配置为将数据包存储在缓冲器中。 处理器被配置为从缓冲器获取分组。 处理器被配置为经由连接端口将数据包发送到交换设备。 处理器被配置为获取连接端口连接到的网络的状态。 处理器被配置为基于网络的状态和预定的分组生成时间来控制要生成的分组的数量。

公开(公告)号：US20140198658A1

公开(公告)日：2014-07-17

申请号：US14215212

申请日：2014-03-17

申请人： FUJITSU LIMITED

发明人： Yuichiro AJIMA ,  Tomohiro INOUE ,  Shinya HIRAMOTO

IPC分类号： H04L12/835 ,  H04L12/26 ,  H04L12/801

CPC分类号： H04L47/30 ,  H04L43/0888 ,  H04L45/28 ,  H04L47/12 ,  H04L47/25 ,  H04L47/283

摘要： Provided is a data communication apparatus which includes a transmission interval calculator configured to calculate an effective transfer speed of the data based on a difference between an actual arrival time at which response data to transmission data transmitted to the other data communication apparatus has arrived and a predictive arrival time calculated by multiplying the number of relay devices passed until the response data from the other data communication apparatus arrives at the data communication apparatus by a transfer delay time necessary to pass through one relay device and a buffer size of the relay device on a communication path of the data, and calculate a transmission interval of transmission data based on the effective transfer speed and a transmission controller configured to perform transmission control of transmission data based on the transmission interval. Thus, congestion control is efficiently implemented in an interconnection network configured as a regular network.

摘要翻译： 提供一种数据通信装置，其包括发送间隔计算器，被配置为基于到达发送到另一数据通信装置的发送数据的响应数据到达的实际到达时间与预测值之间的差来计算数据的有效传送速度 通过乘以通过的中继装置的数量直到来自另一数据通信装置的响应数据到达数据通信装置的通过在通信中通过一个中继装置所需的传送延迟时间和中继装置的缓冲器大小而计算的到达时间 基于有效传送速度计算传输数据的传输间隔，以及传输控制器，被配置为基于传输间隔执行传输数据的传输控制。 因此，在配置为常规网络的互连网络中有效地实现拥塞控制。

公开(公告)号：US20140040558A1

公开(公告)日：2014-02-06

申请号：US14047059

申请日：2013-10-07

申请人： FUJITSU LIMITED

发明人： Yuichiro AJIMA ,  Tomohiro INOUE ,  Shinya HIRAMOTO

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/0802 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0888 ,  G06F15/173

摘要： An information processing apparatus included in a parallel computer system has a memory that holds data and a processor including a cache memory that holds a part of the data held on the memory and a processor core that performs arithmetic operations using the data held on the memory or the cache memory. Moreover, the information processing apparatus has a communication device that determines whether data received from a different information processing apparatus is data that the processor core waits for. When the communication device determines that the received data is data that the processor core waits for, the communication device stores the received data on the cache memory. When the communication device determines that the received data is data that the processor core does not wait for, the communication device stores the received data on the memory.

摘要翻译： 包括在并行计算机系统中的信息处理装置具有保存数据的存储器和包括保存保存在存储器上的数据的一部分的高速缓存存储器的处理器和使用保存在存储器上的数据进行算术运算的处理器核心， 缓存内存。 此外，信息处理装置具有确定从不同的信息处理装置接收的数据是否是处理器核心等待的数据的通信装置。 当通信设备确定接收的数据是处理器核心等待的数据时，通信设备将接收到的数据存储在高速缓冲存储器上。 当通信设备确定接收到的数据是处理器核心不等待的数据时，通信设备将接收到的数据存储在存储器上。

公开(公告)号：US20160112251A1

公开(公告)日：2016-04-21

申请号：US14884142

申请日：2015-10-15

申请人： FUJITSU LIMITED

发明人： Tomohiro INOUE ,  Shun ANDO ,  Shinya HIRAMOTO ,  Masahiro MAEDA ,  Masao YOSHIKAWA

IPC分类号： H04L12/24 ,  H04L12/931 ,  H04L12/801

CPC分类号： H04L41/0672 ,  H04L1/08 ,  H04L1/16 ,  H04L1/20 ,  H04L5/0044 ,  H04L47/13 ,  H04L49/352

摘要： An information processing device includes a transfer unit and an interface unit, the interface unit distributes transmission to a plurality of first lanes, and generate reception information from a plurality of pieces of distribution reception data received through a plurality of second lanes, the transfer unit includes a reception processing unit to extract reception data included in the reception information, and first error information indicating an error in any of the first lanes and a degeneration management unit to generate first degeneration information indicating a use stop lane among the first lanes, based on the first error information, generate second degeneration information indicating a use stop lane among the plurality of second lanes, based on second error information that is output from the interface unit, and cause the transmission processing unit to generate transmission information including the second degeneration information.

摘要翻译： 一种信息处理设备，包括传送单元和接口单元，接口单元将传输分发到多个第一通道，并且从通过多个第二通道接收的多个分发接收数据生成接收信息，所述传送单元包括 接收处理单元，用于提取接收信息中包括的接收数据，以及指示任何第一车道中的错误的第一错误信息和退化管理单元，以基于所述第一车道生成表示所述第一车道中的使用停止车道的第一退化信息， 基于从所述接口单元输出的第二误差信息，生成表示所述多个第二通道中的使用停止通道的第二退化信息，并且使所述发送处理单元生成包括所述第二退化信息的发送信息。

公开(公告)号：US20150256468A1

公开(公告)日：2015-09-10

申请号：US14608389

申请日：2015-01-29

申请人： FUJITSU LIMITED

发明人： Shinya HIRAMOTO ,  Tomohiro INOUE ,  Masahiro MAEDA ,  Shun ANDO

IPC分类号： H04L12/841 ,  H04L12/825 ,  H04L12/801

CPC分类号： H04L47/28 ,  H04L47/11 ,  H04L47/12 ,  H04L47/25

摘要： A control method by an information processing system including a plurality of computers and a plurality of switch devices, the control method includes storing, by a first processor, degeneration information indicating a path in which a transmission rate is decreased and a decreasing ratio of a transmission rate in a first memory when a first switch device which include the first processor detects the path and the first switch device is set as a point of origin; determining, by a second processor, whether a plurality of packets pass through the path, based on the degeneration information when the plurality of packets are transmitted from a computer including the second processor; determining a length of a gap based on the decreasing ratio when it is determined that the plurality of packets pass through the path; and transmitting the plurality of packets with a transmission interval based on the length.

摘要翻译： 一种由包括多个计算机和多个开关装置的信息处理系统的控制方法，所述控制方法包括：由第一处理器存储表示传输速率降低的路径的退化信息和传输的减少比率 当包括第一处理器的第一开关装置检测到路径并且将第一开关装置设置为原点时，第一存储器中的速率; 当从包括所述第二处理器的计算机发送所述多个分组时，基于所述退化信息，由所述第二处理器确定所述多个分组是否通过所述路径; 当确定所述多个分组通过所述路径时，基于所述递减比确定间隙的长度; 以及基于所述长度以传输间隔发送所述多个分组。

公开(公告)号：US20150195191A1

公开(公告)日：2015-07-09

申请号：US14664071

申请日：2015-03-20

申请人： FUJITSU LIMITED

发明人： Tomohiro INOUE ,  Yuichiro AJIMA ,  Shinya HIRAMOTO ,  Masahiro MAEDA ,  Shun ANDO ,  Yuta TOYODA

IPC分类号： H04L12/707 ,  H04L12/721

CPC分类号： H04L45/22 ,  G06F15/17362 ,  H04L41/0663 ,  H04L41/0677 ,  H04L45/14

摘要： A parallel computer includes a plurality of nodes. Each of the nodes includes a router directly or indirectly connected to each of the other nodes and a network interface connected to an external network of the parallel computer. The network interface includes a storage unit that holds detour route information indicating a detour route corresponding to a communication route from a node in which the network interface is included to another node. The network interface further includes a reception processing unit that, when the network interface receives data destined to one node of the parallel computer from the external network, sets detour route information corresponding to a communication route from the node in which the network interface is included to the destination node of the data for the data and transmits the data for which the detour route information is set to the destination node.

摘要翻译： 并行计算机包括多个节点。 每个节点包括直接或间接连接到每个其他节点的路由器以及连接到并行计算机的外部网络的网络接口。 网络接口包括存储单元，其保存迂回路由信息，该迂回路由信息指示与从其中包括网络接口的节点到另一个节点的通信路由相对应的迂回路由。 网络接口还包括：接收处理单元，当所述网络接口从外部网络接收目的地为所述并行计算机的一个节点的数据时，将与通信路由对应的迂回路由信息从包含所述网络接口的节点设置到 数据的目的地节点，并将其中设置了迂回路由信息的数据发送到目的地节点。

公开(公告)号：US20140019512A1

公开(公告)日：2014-01-16

申请号：US14032687

申请日：2013-09-20

申请人： FUJITSU LIMITED

发明人： Yuichiro AJIMA ,  Tomohiro INOUE ,  Shinya HIRAMOTO

IPC分类号： H04L29/08

CPC分类号： H04L67/10 ,  G06F15/17375 ,  G06F15/17381 ,  H04L49/25

摘要： A parallel computing system includes: each computing node including: a first channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; a second channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; and a computational processor receiving data which the first or second channel has received, and transferring processed data to a subsequent node; an input-output node including: a third channel receiving data which the first channel or the computational processor of a preceding node transfers; a fourth channel receiving data which the first channel or the computational processor of a preceding computing node transfers, and transferring the received data to the second channel of a subsequent computing node; and an input-output processor receiving data which the third channel has received, and transferring inputted and outputted data to the first channel of a subsequent computing node.

摘要翻译： 并行计算系统包括：每个计算节点包括：第一信道接收先前节点传送的数据，并将接收到的数据传送到后续节点; 第二信道接收先前节点传送的数据，并将接收到的数据传送到后续节点; 以及计算处理器，接收所述第一或第二信道已经接收到的数据，并将处理的数据传送到后续节点; 输入输出节点，包括：第三通道，其接收先前节点的第一通道或计算处理器传送的数据; 第四信道，接收先前计算节点的第一信道或计算处理器传送的数据，并将所接收的数据传送到后续计算节点的第二信道; 以及接收第三信道已经接收的数据的输入输出处理器，并将输入和输出的数据传送到后续计算节点的第一信道。