公开(公告)号：US09749222B2

公开(公告)日：2017-08-29

申请号：US14664071

申请日：2015-03-20

申请人： FUJITSU LIMITED

发明人： Tomohiro Inoue ,  Yuichiro Ajima ,  Shinya Hiramoto ,  Masahiro Maeda ,  Shun Ando ,  Yuta Toyoda

IPC分类号： H04L12/707 ,  H04L12/24 ,  G06F15/173 ,  H04L12/721

CPC分类号： H04L45/22 ,  G06F15/17362 ,  H04L41/0663 ,  H04L41/0677 ,  H04L45/14

摘要： A parallel computer includes a plurality of nodes. Each of the nodes includes a router directly or indirectly connected to each of the other nodes and a network interface connected to an external network of the parallel computer. The network interface includes a storage unit that holds detour route information indicating a detour route corresponding to a communication route from a node in which the network interface is included to another node. The network interface further includes a reception processing unit that, when the network interface receives data destined to one node of the parallel computer from the external network, sets detour route information corresponding to a communication route from the node in which the network interface is included to the destination node of the data for the data and transmits the data for which the detour route information is set to the destination node.

公开(公告)号：US09426080B2

公开(公告)日：2016-08-23

申请号：US14215212

申请日：2014-03-17

申请人： FUJITSU LIMITED

发明人： Yuichiro Ajima ,  Tomohiro Inoue ,  Shinya Hiramoto

IPC分类号： H04L12/835 ,  H04L12/26 ,  H04L12/801 ,  H04L12/825 ,  H04L12/841 ,  H04L12/703

CPC分类号： H04L47/30 ,  H04L43/0888 ,  H04L45/28 ,  H04L47/12 ,  H04L47/25 ,  H04L47/283

摘要： Provided is a data communication apparatus which includes a transmission interval calculator configured to calculate an effective transfer speed of the data based on a difference between an actual arrival time at which response data to transmission data transmitted to the other data communication apparatus has arrived and a predictive arrival time calculated by multiplying the number of relay devices passed until the response data from the other data communication apparatus arrives at the data communication apparatus by a transfer delay time necessary to pass through one relay device and a buffer size of the relay device on a communication path of the data, and calculate a transmission interval of transmission data based on the effective transfer speed and a transmission controller configured to perform transmission control of transmission data based on the transmission interval. Thus, congestion control is efficiently implemented in an interconnection network configured as a regular network.

摘要翻译： 提供一种数据通信装置，其包括发送间隔计算器，被配置为基于到达发送到另一数据通信装置的发送数据的响应数据到达的实际到达时间与预测值之间的差来计算数据的有效传送速度 通过乘以通过的中继装置的数量直到来自另一数据通信装置的响应数据到达数据通信装置的通过一个中继装置所需的传送延迟时间和中继装置在通信中的缓冲器大小而计算的到达时间 基于有效传送速度计算传输数据的传输间隔，以及传输控制器，被配置为基于传输间隔执行传输数据的传输控制。 因此，在配置为常规网络的互连网络中有效地实现拥塞控制。

公开(公告)号：US20160062943A1

公开(公告)日：2016-03-03

申请号：US14833382

申请日：2015-08-24

申请人： FUJITSU LIMITED

发明人： Atsuyuki NIKAMI ,  Toshiyuki Shimizu ,  Tomohiro Inoue

IPC分类号： G06F13/42 ,  G06F13/40

CPC分类号： G06F13/4286 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

摘要： First and second apparatuses are connected with each other through a communication path provided with a plurality of lanes used for data transfer that is performed between the first and second apparatuses. Prior to data transfer, transfer-control information is exchanged between the first and second apparatuses according to a predetermined communication protocol. Upon detecting transfer-control information, the first apparatus notifies the second apparatus of a lane-control instruction to increase a second lane-counter indicating a number of lanes used by the second apparatus, and increases a first lane-counter indicating a number of lanes used by the first apparatus so that the first lane-counter is greater than a number of lanes that have been used when detecting the transfer-control information. Upon detecting the lane-control instruction, the second apparatus increases the second lane-counter so that the second lane-counter is greater than a number of lanes that have been used when detecting the instruction.

摘要翻译： 第一和第二装置通过设置有在第一和第二装置之间执行的用于数据传送的多个通道的通信路径相互连接。 在数据传送之前，根据预定的通信协议在第一和第二设备之间交换传送控制信息。 在检测到传送控制信息时，第一装置向第二装置通知车道控制指令，以增加指示第二装置使用的车道数量的第二通道计数器，并增加指示车道数的第一通道计数器 使得第一通道计数器大于在检测转移控制信息时已经使用的通道数。 在检测到车道控制指令时，第二装置增加第二通道计数器，使得第二通道计数器大于在检测到指令时已经使用的通道数。

公开(公告)号：US20150178211A1

公开(公告)日：2015-06-25

申请号：US14640559

申请日：2015-03-06

申请人： FUJITSU LIMITED

发明人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue ,  Yuta Toyoda ,  Shun Ando ,  Masahiro Maeda

IPC分类号： G06F12/08

CPC分类号： G06F12/0833 ,  G06F12/0806 ,  G06F13/385 ,  G06F2212/2515 ,  G06F2212/621 ,  G06F2213/3808

摘要： An information processing apparatus includes: storage devices that store data; a data generation unit that generates padding-added data by adding padding to the data, based on adjustment information included in received data; and a storage processing unit that stores the padding-added data generated by the data generation unit in the storage devices. It is possible to shorten a latency even when non-aligned data is received.

摘要翻译： 信息处理设备包括：存储数据的存储设备; 数据生成单元，通过根据接收到的数据中包含的调整信息，通过向数据添加填充来生成填充附加数据; 以及存储处理单元，其将由数据生成单元生成的填充附加数据存储在存储装置中。 即使接收到不对齐的数据，也可以缩短延迟。

公开(公告)号：US09542313B2

公开(公告)日：2017-01-10

申请号：US14540381

申请日：2014-11-13

申请人： FUJITSU LIMITED

发明人： Shinya Hiramoto ,  Tomohiro Inoue ,  Masahiro Maeda ,  Shun Ando ,  Yuta Toyoda

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F9/52

CPC分类号： G06F12/0804 ,  G06F9/526 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0842 ,  G06F2212/1024 ,  G06F2212/283

摘要： A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.

摘要翻译： 并行计算机系统包括信息处理设备，每个信息处理设备包括执行通信的通信控制设备，存储数据的主存储器和耦合到通信控制设备和主存储器的算术处理设备， 信息处理设备通过相应的通信控制设备通过网络彼此耦合，其中所述算术处理设备包括高速缓存存储器和高速缓存控制器，所述高速缓存控制器对存储所述高速缓冲存储器的高速缓冲存储器上的目标数据执行原子操作 当通信控制装置输出用于请求原子操作的原子操作请求时，原子操作不被划分为更小的操作，并将通过执行原子操作获得的结果通知给通信控制装置， 缓存内存。

公开(公告)号：US09385961B2

公开(公告)日：2016-07-05

申请号：US14031775

申请日：2013-09-19

申请人： FUJITSU LIMITED

发明人： Shinya Hiramoto ,  Yuji Oinaga ,  Yuichiro Ajima ,  Tomohiro Inoue

IPC分类号： H04J3/16 ,  H04L12/805 ,  H04L12/825 ,  G06F15/173

CPC分类号： H04L47/365 ,  G06F15/173 ,  H04L47/25

摘要： A parallel computing device includes a plurality of communicatively interconnected nodes for executing an arithmetic process. Each of the plurality of nodes includes: a measurement unit configured to measure a communication bandwidth up to a destination node based on a communication scheme among the nodes, and a control unit configured to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement unit.

摘要翻译： 并行计算设备包括用于执行算术处理的多个通信互连的节点。 所述多个节点中的每一个包括：测量单元，被配置为基于所述节点之间的通信方案来测量直到目的地节点的通信带宽;以及控制单元，被配置为根据所述节点控制发送到所述目的地节点的分组的大小 由测量单元测量的通信带宽。

公开(公告)号：US20140023090A1

公开(公告)日：2014-01-23

申请号：US14031775

申请日：2013-09-19

申请人： FUJITSU LIMITED

发明人： Shinya Hiramoto ,  Yuji Oinaga ,  Yuichiro Ajima ,  Tomohiro Inoue

IPC分类号： H04L12/805

CPC分类号： H04L47/365 ,  G06F15/173 ,  H04L47/25

摘要： A parallel computing device includes a plurality of communicatively interconnected nodes for executing an arithmetic process. Each of the plurality of nodes includes: a measurement unit configured to measure a communication bandwidth up to a destination node based on a communication scheme among the nodes, and a control unit configured to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement unit.

摘要翻译： 并行计算设备包括用于执行算术处理的多个通信互连的节点。 所述多个节点中的每一个包括：测量单元，被配置为基于所述节点之间的通信方案来测量直到目的地节点的通信带宽;以及控制单元，被配置为根据所述节点控制发送到所述目的地节点的分组的大小 由测量单元测量的通信带宽。

公开(公告)号：US09342473B2

公开(公告)日：2016-05-17

申请号：US13921327

申请日：2013-06-19

申请人： FUJITSU LIMITED

发明人： Shun Ando ,  Shinya Hiramoto ,  Tomohiro Inoue ,  Yuta Toyoda ,  Masahiro Maeda ,  Yuichiro Ajima

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4022

摘要： A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors.

摘要翻译： 并行计算机系统包括多个处理器，包括第一处理器和多个第二处理器; 以及设置有多个端口的交叉开关; 其中所述第一处理器向所述多个端口中的第一端口发送数据，并且在所述多个第二处理器不能将数据发送到所述第一端口的情况下将待机时间信息发送到所述第一端口，尽管接收到来自 第一端口和第一端口接收待机时间信息，并且在待机时间过去之后，选择多个第二处理器中的一个。

公开(公告)号：US20160112312A1

公开(公告)日：2016-04-21

申请号：US14875994

申请日：2015-10-06

申请人： FUJITSU LIMITED

发明人： Shinya HIRAMOTO ,  Tomohiro Inoue ,  Shun Ando ,  Masahiro Maeda ,  Masao Yoshikawa

IPC分类号： H04L12/741 ,  H04L12/861

CPC分类号： H04L45/74 ,  H04L49/9005

摘要： A communication apparatus includes a connection port and a processor. The connection port is connected to a switch apparatus. The processor is configured to acquire data to be transmitted to an external apparatus. The processor is configured to generate a packet destined to the external apparatus. The packet contains the data. The processor is configured to store the packet in a buffer. The processor is configured to acquire the packet from the buffer. The processor is configured to transmit the packet to the switch apparatus via the connection port. The processor is configured to acquire a state of a network to which the connection port is connected. The processor is configured to control, on basis of the state of the network and a predetermined packet generation time, a number of packets to be generated.

摘要翻译： 通信装置包括连接端口和处理器。 连接端口连接到开关装置。 处理器被配置为获取要发送到外部设备的数据。 处理器被配置为生成去往外部设备的分组。 数据包包含数据。 处理器被配置为将数据包存储在缓冲器中。 处理器被配置为从缓冲器获取分组。 处理器被配置为经由连接端口将数据包发送到交换设备。 处理器被配置为获取连接端口连接到的网络的状态。 处理器被配置为基于网络的状态和预定的分组生成时间来控制要生成的分组的数量。

公开(公告)号：US09164907B2

公开(公告)日：2015-10-20

申请号：US14047059

申请日：2013-10-07

申请人： FUJITSU LIMITED

发明人： Yuichiro Ajima ,  Tomohiro Inoue ,  Shinya Hiramoto

IPC分类号： G06F12/08 ,  G06F15/173

CPC分类号： G06F12/0815 ,  G06F12/0802 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0888 ,  G06F15/173

摘要： An information processing apparatus included in a parallel computer system has a memory that holds data and a processor including a cache memory that holds a part of the data held on the memory and a processor core that performs arithmetic operations using the data held on the memory or the cache memory. Moreover, the information processing apparatus has a communication device that determines whether data received from a different information processing apparatus is data that the processor core waits for. When the communication device determines that the received data is data that the processor core waits for, the communication device stores the received data on the cache memory. When the communication device determines that the received data is data that the processor core does not wait for, the communication device stores the received data on the memory.

摘要翻译： 包括在并行计算机系统中的信息处理装置具有保存数据的存储器和包括保存保存在存储器上的数据的一部分的高速缓存存储器的处理器和使用保存在存储器上的数据进行算术运算的处理器核心， 缓存内存。 此外，信息处理装置具有确定从不同的信息处理装置接收的数据是否是处理器核心等待的数据的通信装置。 当通信设备确定接收的数据是处理器核心等待的数据时，通信设备将接收到的数据存储在高速缓冲存储器上。 当通信设备确定接收到的数据是处理器核心不等待的数据时，通信设备将接收到的数据存储在存储器上。