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公开(公告)号：US11537916B2
公开(公告)日：2022-12-27
申请号：US16898484
申请日：2020-06-11
申请人： FUJITSU LIMITED
摘要： An optimization apparatus includes a memory; and a processor coupled to the memory and the processor configured to: compute a local solution for a combinatorial optimization problem based on a first evaluation function representing the combinatorial optimization problem, select a state variable group targeted by partial problems from the plurality of state variables based on a first state variable whose value at the local solution is a predetermined value among the plurality of state variables included in the first evaluation function, a weight coefficient representing a magnitude of an interaction between the plurality of state variables held in a storage unit, and input selection region information, search a ground state for a second evaluation function representing the partial problems for the selected state variable group, and generate a whole solution by updating the local solution based on the partial solutions acquired by the ground state search.
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公开(公告)号：US20210382960A1
公开(公告)日：2021-12-09
申请号：US17189312
申请日：2021-03-02
申请人： FUJITSU LIMITED
摘要： An apparatus includes: a communication circuit configured to communicate with a search circuit configured to search for a solution minimizing a value of an objective function; and a processing circuit configured to: cause the search circuit to execute the search by using each of a first state and a second state as a starting point, the search being configured to change a value of a predetermined external parameter affecting an increase or decrease in the value of the objective function in a direction of promoting an increase in the value of the objective function; acquire a first state group obtained using the first state and a second state group obtained using the second state; determine a third state among unsearched states by using the first state group and the second state group; and cause the search circuit to execute the search by using the third state as the starting point.
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公开(公告)号：US10103870B2
公开(公告)日：2018-10-16
申请号：US15889272
申请日：2018-02-06
申请人： FUJITSU LIMITED
发明人： Takayuki Shibasaki
摘要： A CDR circuit includes a data-determination-circuit to determine a value of a data-signal, based on a first comparison-result of comparing the data-signal with first threshold-values at a timing of a clock-signal, a comparison-circuit to compare the data-signal with a second threshold-value at the timing to generate a second comparison-result, a phase-detection-circuit to detect data-patterns in which first to third symbols are temporally consecutive, based on a determination-result, the data-patterns forming that a value of the second symbol is larger than the first symbol and smaller than the third symbol, or the in value of the second symbol is smaller than the first symbol and larger than the third symbol, wherein the phase-detection-circuit generates a phase-difference-signal for controlling a phase of the clock-signal to advance or delay, based on the second comparison-result at the second symbol, and a phase-adjustment-circuit to adjust the phase of the clock-signal based on the phase-difference-signal.
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公开(公告)号：US20170026047A1
公开(公告)日：2017-01-26
申请号：US15185964
申请日：2016-06-17
申请人： FUJITSU LIMITED
发明人： Takayuki Shibasaki
CPC分类号： H03L7/087 , H03L7/0807 , H03L7/089 , H03L7/091 , H03L7/095 , H03L7/1072 , H04L7/0004 , H04L7/0087 , H04L7/033 , H04L7/06
摘要： A determination circuit receives an input data signal and determines a value of the input data signal when a logic level of a sampling clock changes. A sampling clock generation circuit generates the sampling clock on the basis of the input data signal, generates a frequency adjustment value on the basis of the frequency difference between the sampling clock and the input data signal, and adjusts the frequency of the sampling clock on the basis of the frequency adjustment value. A frequency pull-in control circuit performs integration on frequency adjustment values and obtains an integral value in an individual time period. When the integral value reaches a threshold before a single time period elapses, the frequency pull-in control circuit outputs a reset signal that causes the sampling clock generation circuit to output an initial value of the frequency adjustment value until the time period elapses.
摘要翻译： 当采样时钟的逻辑电平变化时，确定电路接收输入数据信号并确定输入数据信号的值。 采样时钟产生电路基于输入数据信号产生采样时钟，根据采样时钟和输入数据信号之间的频率差产生频率调整值，并调整采样时钟的频率 频率调整值的基础。 频率拉入控制电路对频率调整值进行积分，并在各个时间段内获得积分值。 当积分值在单个时间间隔过去之前达到阈值时，频率引入控制电路输出使得采样时钟产生电路输出频率调整值的初始值直到经过时间段的复位信号。
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5.发明授权Interpolation circuit, reception circuit and method of generating interpolated data 有权插值电路，接收电路和生成内插数据的方法公开(公告)号：US08848835B2
公开(公告)日：2014-09-30
申请号：US13827726
申请日：2013-03-14
申请人： Fujitsu Limited
发明人： Takayuki Shibasaki
摘要： An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.
摘要翻译： 内插电路包括：生成电路，被配置为基于多个输入数据按时间顺序生成内插数据; 第一模拟数字转换器，被配置为将内插数据的数据点处的第一内插数据转换为第一数字数据; 以及第二模拟数字转换器，其被配置为将变化点处的第二内插数据转换成所述内插数据的第二数字数据，所述第二模拟数字转换器的第二数量的量化比特小于所述第一模拟数字转换器的第一数量的量化比特 数字转换器。
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公开(公告)号：US20140286381A1
公开(公告)日：2014-09-25
申请号：US14170901
申请日：2014-02-03
申请人： FUJITSU LIMITED
发明人： Takayuki Shibasaki
IPC分类号： H04L1/20
CPC分类号： H04L7/0334 , H03L7/089 , H04L25/03 , H04L25/03057
摘要： In a receiver circuit which can correct a deviation of phase between an input signal and a clock, a sampler detects an amplitude level of the input signal at timing indicated by the clock, a first comparison circuit compares a first and a second amplitude level detected by the sampler at first and second timings, respectively, with a determined threshold, an interpolation circuit calculates an intermediate level that approximates to an amplitude level of the input signal corresponding to an intermediate point between the first and second timings by an interpolation process based on the first and second amplitude levels, a second comparison circuit compares the intermediate level with the determined threshold, and a phase deviation detection circuit detects the deviation of phase between the clock and the input signal on the basis of comparison results obtained by the first and second comparison circuits.
摘要翻译： 在可以校正输入信号和时钟之间的相位偏差的接收机电路中，采样器在由时钟指示的定时处检测输入信号的振幅电平，第一比较电路比较由第一和第二振幅电平检测的第一和第二幅度电平， 第一和第二定时的采样器分别具有确定的阈值，内插电路通过基于第一和第二定时的内插处理来计算近似于与第一和第二定时之间的中间点相对应的输入信号的幅度电平的中间电平 第一和第二幅度电平，第二比较电路将中间电平与确定的阈值进行比较，并且相位偏差检测电路基于通过第一和第二比较获得的比较结果来检测时钟与输入信号之间的相位偏差 电路。
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公开(公告)号：US20190220732A1
公开(公告)日：2019-07-18
申请号：US16240832
申请日：2019-01-07
申请人： FUJITSU LIMITED
CPC分类号： G06N3/0472 , G06N3/0445 , G06N3/086 , G06N7/005
摘要： A transition control unit detects, when stochastically determining based on a temperature, energy changes, and a random number whether to accept any of a plurality of state transitions according to a relative relationship between the energy changes and thermal excitation energy, a minimum value among the energy changes. The transition control unit then subtracts, when the minimum value is positive, an offset obtained by multiplying the minimum value by a value M that is greater than 0 and less than or equal to 1 from each of the energy changes corresponding to the plurality of state transitions.
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公开(公告)号：US10326582B2
公开(公告)日：2019-06-18
申请号：US15922985
申请日：2018-03-16
申请人： FUJITSU LIMITED
发明人： Yasufumi Sakai , Takayuki Shibasaki
摘要： An optical transmitter includes: an optical modulator, a phase adjustment circuit, first and second synchronization circuits, and first and second drive circuits. The optical modulator includes a first modulation area and a second modulation area that is provided at output side of the first modulation area. The phase adjustment circuit adjusts a phase of a first clock signal so as to generate a second clock signal. The first and second synchronization circuits respectively output first and second electric signals in synchronization with the first and second clock signals. The first and second drive circuits respectively drive the first and second modulation areas with the first and second electric signals.
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公开(公告)号：US10103911B2
公开(公告)日：2018-10-16
申请号：US15913122
申请日：2018-03-06
申请人： FUJITSU LIMITED
发明人： Takayuki Shibasaki
摘要： A comparator circuit outputs a comparison result obtained by comparing a data signal with a threshold whose magnitude is adjusted based on a first offset value at a timing synchronized with a second clock signal whose phase is adjusted based on a difference in phase between the data signal and a first clock signal and a second offset value. An eye monitor circuit thins comparison results obtained in a clock data recovery (CDR) circuit for individual symbols of the data signal by comparing the data signal with a threshold, selects a comparison result corresponding to a symbol for which the comparison result is obtained by the comparator circuit, determines, by comparing the selected comparison result with the comparison result obtained by the comparator circuit, whether or not an error has occurred due to the first or second offset value, and outputs the number of times the error has occurred.
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公开(公告)号：US20180227114A1
公开(公告)日：2018-08-09
申请号：US15881903
申请日：2018-01-29
申请人： FUJITSU LIMITED
CPC分类号： H04L7/0037 , H03L7/0807 , H03L7/085 , H03L7/087 , H03L7/099 , H04L7/0079 , H04L7/033
摘要： A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.
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