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公开(公告)号：US20150200197A1
公开(公告)日：2015-07-16
申请号：US14579394
申请日：2014-12-22
发明人： Hitoshi Saito
IPC分类号： H01L27/115 , H01L27/108 , H01L49/02
CPC分类号： H01L27/11502 , H01L27/0805 , H01L27/108 , H01L27/11507 , H01L27/11509 , H01L28/56 , H01L28/60
摘要： An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.
摘要翻译： 化合物半导体器件的实施例包括：第一下电极; 第一下电极上的第一绝缘膜; 在所述第一绝缘膜上方的第一上电极; 与第一下电极分离的第二下电极; 在所述第二下电极上的第二绝缘膜; 第二绝缘膜上的第三绝缘膜; 以及位于第三绝缘膜上的第二上电极。 第一绝缘膜的厚度与第三绝缘膜的厚度基本相同，平面图中的第三绝缘膜的轮廓在平面图中位于第二绝缘膜的轮廓之外，第二上部的轮廓 平面图中的电极在平面图中位于第二绝缘膜的轮廓内。
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公开(公告)号：US09081050B2
公开(公告)日：2015-07-14
申请号：US14103310
申请日：2013-12-11
发明人： Akihiko Okutsu , Hitoshi Saito , Yoshiaki Okano
CPC分类号： G01R31/275 , G01R31/2601 , G01R31/2884 , H01L22/32 , H01L23/522 , H01L23/564 , H01L23/585 , H01L2224/05554 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.
摘要翻译： 半导体器件包括：半导体衬底，包括元件区域，内部密封件和外部密封件，所述元件区域，内部密封件和外部密封件分别形成在所述元件区域上并具有第一开口部分和第二开口部分，所述多层互连结构分别形成在所述衬底上 并且堆叠多个层间绝缘膜，每个层间绝缘膜包括布线层，形成在包括在多层互连结构中的第一层间绝缘膜和第二层间绝缘膜之间的防潮膜，第一部分从 所述防潮膜的第一面通过所述第一开口部，所述第二部分从所述防湿膜的第二侧延伸并穿过所述第二开口部;以及布线图案，其包括穿过所述防潮膜的通孔塞 并且连接第一部分和第二部分。
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公开(公告)号：US20140097861A1
公开(公告)日：2014-04-10
申请号：US14103310
申请日：2013-12-11
发明人： Akihiko Okutsu , Hitoshi Saito , Yoshiaki Okano
CPC分类号： G01R31/275 , G01R31/2601 , G01R31/2884 , H01L22/32 , H01L23/522 , H01L23/564 , H01L23/585 , H01L2224/05554 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.
摘要翻译： 半导体器件包括：半导体衬底，包括元件区域，内部密封件和外部密封件，所述元件区域，内部密封件和外部密封件分别形成在所述元件区域上并具有第一开口部分和第二开口部分，所述多层互连结构分别形成在所述衬底上 并且堆叠多个层间绝缘膜，每个层间绝缘膜包括布线层，形成在包括在多层互连结构中的第一层间绝缘膜和第二层间绝缘膜之间的防湿膜，第一部分从 所述防潮膜的第一面通过所述第一开口部，所述第二部分从所述防湿膜的第二侧延伸并穿过所述第二开口部;以及布线图案，其包括穿过所述防潮膜的通孔塞 并且连接第一部分和第二部分。
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公开(公告)号：US20160043165A1
公开(公告)日：2016-02-11
申请号：US14797405
申请日：2015-07-13
发明人： Hitoshi Saito , Wensheng Wang
CPC分类号： H01L28/75 , H01L27/0629 , H01L27/11507 , H01L27/11509 , H01L28/87
摘要： A semiconductor device includes: a semiconductor substrate; a base above the semiconductor substrate; a first conductive plug in the base; a memory cell region in the base; and a logic circuit region connected to the memory cell region, the logic circuit including a first capacitor. The first capacitor includes: a first bottom electrode, a part of a lower surface of the first bottom electrode being in contact with the first conductive plug; a first insulating film on the first bottom electrode; and a first top electrode on the first insulating film. The first top electrode is spaced apart from the first conductive plug in planar view.
摘要翻译： 半导体器件包括：半导体衬底; 在半导体衬底上方的基底; 基座中的第一导电插头; 基底中的记忆单元区域; 以及与存储单元区域连接的逻辑电路区域，所述逻辑电路包括第一电容器。 第一电容器包括：第一底部电极，第一底部电极的下表面的一部分与第一导电插塞接触; 在第一底部电极上的第一绝缘膜; 以及第一绝缘膜上的第一顶部电极。 在平面视图中，第一顶部电极与第一导电插塞间隔开。
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公开(公告)号：US09147688B2
公开(公告)日：2015-09-29
申请号：US14579394
申请日：2014-12-22
发明人： Hitoshi Saito
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00 , H01L27/115 , H01L49/02 , H01L27/108
CPC分类号： H01L27/11502 , H01L27/0805 , H01L27/108 , H01L27/11507 , H01L27/11509 , H01L28/56 , H01L28/60
摘要： An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.
摘要翻译： 化合物半导体器件的实施例包括：第一下电极; 第一下电极上的第一绝缘膜; 在所述第一绝缘膜上方的第一上电极; 与第一下电极分离的第二下电极; 在所述第二下电极上的第二绝缘膜; 第二绝缘膜上的第三绝缘膜; 以及位于第三绝缘膜上的第二上电极。 第一绝缘膜的厚度与第三绝缘膜的厚度基本相同，平面图中的第三绝缘膜的轮廓在平面图中位于第二绝缘膜的轮廓之外，第二上部的轮廓 平面图中的电极在平面图中位于第二绝缘膜的轮廓内。
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公开(公告)号：US09472611B2
公开(公告)日：2016-10-18
申请号：US14797405
申请日：2015-07-13
发明人： Hitoshi Saito , Wensheng Wang
IPC分类号： H01L29/76 , H01L49/02 , H01L27/06 , H01L27/115
CPC分类号： H01L28/75 , H01L27/0629 , H01L27/11507 , H01L27/11509 , H01L28/87
摘要： A semiconductor device includes: a semiconductor substrate; a base above the semiconductor substrate; a first conductive plug in the base; a memory cell region in the base; and a logic circuit region connected to the memory cell region, the logic circuit including a first capacitor. The first capacitor includes: a first bottom electrode, a part of a lower surface of the first bottom electrode being in contact with the first conductive plug; a first insulating film on the first bottom electrode; and a first top electrode on the first insulating film. The first top electrode is spaced apart from the first conductive plug in planar view.
摘要翻译： 半导体器件包括：半导体衬底; 在半导体衬底上方的基底; 基座中的第一导电插头; 基底中的记忆单元区域; 以及与存储单元区域连接的逻辑电路区域，所述逻辑电路包括第一电容器。 第一电容器包括：第一底部电极，第一底部电极的下表面的一部分与第一导电插塞接触; 在第一底部电极上的第一绝缘膜; 以及第一绝缘膜上的第一顶部电极。 在平面视图中，第一顶部电极与第一导电插塞间隔开。
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