公开(公告)号：US20090242999A1

公开(公告)日：2009-10-01

申请号：US12355250

申请日：2009-01-16

申请人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

发明人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/31

CPC分类号： H01L21/31604 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

摘要翻译： 包括高k电介质材料的栅极堆叠的封装可以基于以两个沉积工艺的顺序沉积的氮化硅材料来实现，其中第一工艺可以在适度低的工艺 温度，从而钝化敏感表面，而不会不适当地污染它们，而在第二沉积过程中，与传统的ALD或多层沉积技术相比，可以使用适度高的工艺温度来提供增强的材料特性和减小的总循环时间。

公开(公告)号：US07897450B2

公开(公告)日：2011-03-01

申请号：US12355250

申请日：2009-01-16

申请人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

发明人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

IPC分类号： H01L21/8249

CPC分类号： H01L21/31604 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

摘要翻译： 包括高k电介质材料的栅极堆叠的封装可以基于以两个沉积工艺的顺序沉积的氮化硅材料来实现，其中第一工艺可以在适度低的工艺 温度，从而钝化敏感表面，而不会不适当地污染它们，而在第二沉积过程中，与传统的ALD或多层沉积技术相比，可以使用适度高的工艺温度来提供增强的材料特性和减小的总循环时间。

公开(公告)号：US20090246371A1

公开(公告)日：2009-10-01

申请号：US12275304

申请日：2008-11-21

申请人： Fabian Koehler ,  Falk Graetsch

发明人： Fabian Koehler ,  Falk Graetsch

IPC分类号： C23C16/00

CPC分类号： H01L21/31608 ,  H01L21/0223 ,  H01L21/02271 ,  H01L21/31658 ,  H01L21/3185

摘要： A thermally activated batch process is disclosed for forming thin material layers in semiconductor devices including the establishment of an overheating temperature profile prior to actually forming a material layer, for instance, by deposition, so that a gas depletion at the centre of the substrate during the deposition process be compensated for. Thus, enhanced thickness uniformity for thin material layers in the range of 1 to 50 nanometers may be obtained without additional process time or even at a reduced process time.

摘要翻译： 公开了一种用于在半导体器件中形成薄材料层的热激活分批工艺，包括在实际形成材料层之前建立过热温度曲线，例如通过沉积，从而在基板的中心处的气体耗尽 沉积过程得到补偿。 因此，可以获得在1至50纳米范围内的薄材料层的增强的厚度均匀性，而无需额外的处理时间或甚至在缩短的处理时间。

公开(公告)号：US08716149B2

公开(公告)日：2014-05-06

申请号：US13482871

申请日：2012-05-29

申请人： Fabian Koehler ,  Sergej Mutas ,  Dina Triyoso ,  Itasham Hussain

发明人： Fabian Koehler ,  Sergej Mutas ,  Dina Triyoso ,  Itasham Hussain

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/6653 ,  H01L29/6656

摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.

摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有栅极结构的半导体衬底。 执行原子层沉积（ALD）工艺以在栅极结构周围沉积间隔物。 ALD工艺包括跨越半导体衬底的第一前体的交替流动的离子化基团并使氯代硅烷前体流过半导体衬底以沉积间隔物。

公开(公告)号：US20130323923A1

公开(公告)日：2013-12-05

申请号：US13482871

申请日：2012-05-29

申请人： Fabian Koehler ,  Sergej Mutas ,  Dina Triyoso ,  Itasham Hussain

发明人： Fabian Koehler ,  Sergej Mutas ,  Dina Triyoso ,  Itasham Hussain

IPC分类号： H01L21/283 ,  H01L21/31

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/6653 ,  H01L29/6656

摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.

摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有栅极结构的半导体衬底。 执行原子层沉积（ALD）工艺以在栅极结构周围沉积间隔物。 ALD工艺包括跨越半导体衬底的第一前体的交替流动的离子化基团并使氯代硅烷前体流过半导体衬底以沉积间隔物。