-
公开(公告)号：US20120075334A1
公开(公告)日：2012-03-29
申请号：US13246652
申请日：2011-09-27
IPC分类号： G09G5/00
CPC分类号： G06F3/1446 , G06F3/1438 , G09G5/12 , G09G2310/08
摘要： This disclosure describes techniques for controlling a plurality of displays to present an image split across the displays. For example, a host controller is described herein. The host controller receives, from a first display, a first display status that indicates a status of presentation of a first portion of an image by the first display and, from a second display a second display status that indicates a status of presentation of a second portion of the image by the second display. The host controller may compare the first and second display status and, in response to the comparison, communicate to at least one of the first and second displays a display adjustment configured to cause the respective display to adjust presentation of at least one of the first or second portion of the image.
摘要翻译： 本公开描述了用于控制多个显示器以呈现跨越显示器的图像分割的技术。 例如，这里描述了主机控制器。 主机控制器从第一显示器接收指示由第一显示器显示图像的第一部分的状态的第一显示状态，并且从第二显示器接收指示第二显示状态的第二显示状态 图像的第二显示部分。 主机控制器可以比较第一和第二显示状态，并且响应于比较，与第一和第二显示器中的至少一个通信显示调整，其被配置为使得相应的显示器调整第一或第二显示器中的至少一个的显示， 图像的第二部分。
-
公开(公告)号：US08704732B2
公开(公告)日：2014-04-22
申请号：US13246652
申请日：2011-09-27
IPC分类号： G09G5/00
CPC分类号： G06F3/1446 , G06F3/1438 , G09G5/12 , G09G2310/08
摘要： This disclosure describes techniques for controlling a plurality of displays to present an image split across the displays. For example, a host controller is described herein. The host controller receives, from a first display, a first display status that indicates a status of presentation of a first portion of an image by the first display and, from a second display a second display status that indicates a status of presentation of a second portion of the image by the second display. The host controller may compare the first and second display status and, in response to the comparison, communicate to at least one of the first and second displays a display adjustment configured to cause the respective display to adjust presentation of at least one of the first or second portion of the image.
摘要翻译： 本公开描述了用于控制多个显示器以呈现跨越显示器的图像分割的技术。 例如，这里描述了主机控制器。 主机控制器从第一显示器接收指示由第一显示器显示图像的第一部分的状态的第一显示状态，并且从第二显示器接收指示第二显示状态的第二显示状态 图像的第二显示部分。 主机控制器可以比较第一和第二显示状态，并且响应于比较，与第一和第二显示器中的至少一个通信显示调整，其被配置为使得相应的显示器调整第一或第二显示器中的至少一个的显示， 图像的第二部分。
-
公开(公告)号：US07937519B2
公开(公告)日：2011-05-03
申请号：US12500764
申请日：2009-07-10
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译： 缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。 数据字通过数据通道中的活动缓冲区进行定时。 通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。 这种方法允许其他非活动的数据通道保持在省电状态。
-
公开(公告)号：US20090276558A1
公开(公告)日：2009-11-05
申请号：US12500764
申请日：2009-07-10
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译： 缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。 数据字通过数据通道中的活动缓冲区进行定时。 通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。 这种方法允许其他非活动的数据通道保持在省电状态。
-
公开(公告)号：US09432653B2
公开(公告)日：2016-08-30
申请号：US13291013
申请日：2011-11-07
IPC分类号： G06T15/00 , G09G5/00 , G06K9/00 , G06K9/36 , G06K9/32 , G02B27/22 , G02F1/1335 , H04N13/04 , H04N13/00 , G06T11/60 , G06T3/40 , G06T3/60 , G06T7/00 , G09G5/14 , G06T19/00 , H04N21/414 , H04N21/422 , H04N21/4402 , H04N21/81
CPC分类号： H04N13/139 , G02B27/2214 , G06T3/4038 , G06T3/606 , G06T7/593 , G06T11/60 , G06T19/00 , G09G5/14 , H04N13/31 , H04N21/41407 , H04N21/42202 , H04N21/440272 , H04N21/816
摘要： This disclosure describes a host controller configured to combine image data associated with left and right images of a 3D image to control a display consistent with an orientation for the display (e.g., a first and second plurality of active parallax barriers of the display). In response to an orientation for the display, the host controller may combine image data associated with respective left and right images of with a 3D image in a first or second interleaved format to be consistent with the orientation for the display. For example, the host controller may combine the image data to be line-interleaved or pixel interleaved, based on an orientation for the display. In this manner, the display may receive the combined image data and present the 3D image consistent with the orientation for the display, while reducing processing performed by the display to present the 3D image.
摘要翻译： 该公开内容描述了主机控制器，被配置为组合与3D图像的左图像和右图像相关联的图像数据，以控制与用于显示器的定向（例如，显示器的第一和第二多个有效视差屏障）一致的显示。 响应于显示的方向，主控制器可以将与相应的左图像和右图像相关联的图像数据与第一或第二交错格式的3D图像组合以与显示的方向一致。 例如，主机控制器可以基于显示器的取向来组合要进行行交错或像素交织的图像数据。 以这种方式，显示器可以接收组合的图像数据并呈现与显示方向一致的3D图像，同时减少显示器执行的呈现3D图像的处理。
-
公开(公告)号：US08223796B2
公开(公告)日：2012-07-17
申请号：US12141358
申请日：2008-06-18
IPC分类号： H04J3/16
CPC分类号： G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
摘要： A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC.
摘要翻译： 图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合为显示串行接口定义的协议的半双工双向串行链路和符合协议的单向串行链路 到为相机串行接口定义的兼容协议。 GMIC根据通过半双工双向串行链路的主机的协议接收数据包，并处理这些数据包。 GMIC根据协议将数据包通过单向串行链路发送到主机。 来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包，以在主机的内存中启动内存操作。 GMIC可以根据显示串行接口协议通过双向串行链路连接到显示器，并且可以根据相机串行接口通过单向串行链路和双向控制链路连接到相机，使得主机 通过GMIC间接控制显示和相机。
-
公开(公告)号：US20070079047A1
公开(公告)日：2007-04-05
申请号：US11536365
申请日：2006-09-28
IPC分类号： G06F13/00
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
摘要翻译： 缓冲器与多通道串行数据总线的多个数据通道中的每一条相关联。 数据字通过数据通道中的活动缓冲区进行定时。 通过活动数据通道的缓冲器定时的字被合并到并行总线上，使得来自每个活动数据通道的数据字以预定义的数据通道重复序列合并到并行总线上。 这种方法允许其他非活动数据通道保持在功率节省状态。
-
公开(公告)号：US20130010168A1
公开(公告)日：2013-01-10
申请号：US13495518
申请日：2012-06-13
CPC分类号： G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
摘要： A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.
摘要翻译： 图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合显示串行接口协议的半双工双向串行链路和符合相机的单向串行链路 串行接口协议 GMIC通过半双工双向串行链路从主机接收数据包，并处理这些数据包。 GMIC通过单向串行链路发送数据包。 来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包以启动主机存储器操作，并且可以通过双向串行链路连接到显示器，并且可以通过单向串行链路和允许主机的双向控制链路连接到摄像机 来控制显示器和相机。
-
公开(公告)号：US07929648B2
公开(公告)日：2011-04-19
申请号：US11278221
申请日：2006-03-31
IPC分类号： H04L27/06
CPC分类号： H04L7/0083
摘要： An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.
摘要翻译： 错误检测装置和方法比较第一硬连线值（例如第一时钟阈值）和第二硬连线值（例如第二时钟阈值），并且基于第一时钟阈值的比较生成时钟信号中存在错误的指示 硬连线值和第二个硬连线值到时钟信号。 如果检测到错误，则错误检测装置将例如中断时钟恢复逻辑以采取适当的动作来恢复生成时钟信号的时钟产生电路。 时钟信号可以基于例如可由外部源时钟提供的参考时钟信号或任何其它合适的源来产生。
-
10.发明申请COMMUNICATION PROTOCOL FOR SHARING MEMORY RESOURCES BETWEEN COMPONENTS OF A DEVICE 有权用于在设备的组件之间共享存储资源的通信协议公开(公告)号：US20100185800A1
公开(公告)日：2010-07-22
申请号：US12356898
申请日：2009-01-21
IPC分类号： G06F13/00
CPC分类号： G06F13/404
摘要： In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units which are sent over the interconnect to initiate memory access operations. The approach may also be used to allow for a degree of communication between device components.
摘要翻译： 在诸如蜂窝电话的设备中，在诸如具有存储器资源的集成电路的组件之间启用存储器资源共享。 这可以通过在组件之间提供互连并构建通过互连发送以发起存储器访问操作的事务单元来实现。 该方法还可以用于允许设备组件之间的一定程度的通信。
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.022 秒)
