Method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a top cladding
    1.
    发明授权
    Method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a top cladding 有权
    通过选择顶部包层的波导芯宽度来控制波导双折射的方法和装置

    公开(公告)号:US07609917B2

    公开(公告)日:2009-10-27

    申请号:US12079930

    申请日:2008-03-28

    IPC分类号: G02B6/12 G02B6/10 G02B6/34

    CPC分类号: G02B6/12023 G02B6/126

    摘要: A method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a tuned top clad is described herein. In one example, a dopant concentration within a top cladding material is between 3-6% (wt.). Given a tuned top cladding composition, a width of the waveguide core is pre-selected such that birefringence is minimized, i.e., a zero, or near zero. The desirable width of the waveguide core is determined by calculating the distribution of stress in the top cladding over a change in temperature. From this distribution of stress, a relationship between the polarization dependent wavelength and variable widths of the waveguide in the arrayed waveguide grating are determined. This relationship determines a zero value, or near zero value, of polarization dependent wavelength for a given range of waveguide widths. Accordingly, the width of the waveguide may be selected such that the polarization dependent wavelength is minimized.

    摘要翻译: 本文描述了通过选择用于调谐顶部包层的波导芯宽度来控制波导双折射的方法和装置。 在一个实例中,顶部包层材料内的掺杂剂浓度在3-6%(重量)之间。 给定一个调整的顶部包层组成,预先选择波导芯的宽度,使得双折射最小化,即零或接近零。 通过计算在顶部包层中的应力在温度变化中的分布来确定波导芯的期望宽度。 根据这种应力分布,确定阵列波导光栅中波导的偏振相关波长与可变宽度之间的关系。 对于给定的波导宽度范围,该关系确定偏振相关波长的零值或近零值。 因此,可以选择波导的宽度使得偏振相关波长最小化。

    Method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a top clad
    2.
    发明授权
    Method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a top clad 有权
    通过选择顶部包层的波导芯宽度来控制波导双折射的方法和装置

    公开(公告)号:US06850670B2

    公开(公告)日:2005-02-01

    申请号:US09894049

    申请日:2001-06-28

    IPC分类号: G02B6/12 G02B6/126 G02B6/34

    CPC分类号: G02B6/126 G02B2006/121

    摘要: A method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a tuned top clad is described herein. A tuned top cladding describes a pre-existing dopant concentration within a top cladding material. Given a tuned top cladding composition, a width of the waveguide core is pre-selected such that birefringence is minimized, i.e., a zero, or near zero. The desirable width of the waveguide core is determined by calculating the distribution of stress in the top cladding over a change in temperature. From this distribution of stress, a relationship between the polarization dependent wavelength and variable widths of the waveguide in the arrayed waveguide grating are determined. This relationship determines a zero value, or near zero value, of polarization dependent wavelength for a given range of waveguide widths. Accordingly, the width of the waveguide may be selected such that the polarization dependent wavelength is minimized.

    摘要翻译: 本文描述了通过选择用于调谐顶部包层的波导芯宽度来控制波导双折射的方法和装置。 调谐的顶部包层描述了顶部包层材料中预先存在的掺杂剂浓度。 给定一个调整的顶部包层组成,预先选择波导芯的宽度,使得双折射最小化,即零或接近零。 通过计算在顶部包层中的应力在温度变化中的分布来确定波导芯的期望宽度。 根据这种应力分布,确定阵列波导光栅中波导的偏振相关波长与可变宽度之间的关系。 对于给定的波导宽度范围,该关系确定偏振相关波长的零值或近零值。 因此,可以选择波导的宽度使得偏振相关波长最小化。

    Method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a top cladding
    3.
    发明申请
    Method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a top cladding 有权
    通过选择顶部包层的波导芯宽度来控制波导双折射的方法和装置

    公开(公告)号:US20080240655A1

    公开(公告)日:2008-10-02

    申请号:US12079930

    申请日:2008-03-28

    IPC分类号: G02B6/34 G02B6/10

    CPC分类号: G02B6/12023 G02B6/126

    摘要: A method and apparatus for controlling waveguide birefringence by selection of a waveguide core width for a tuned top clad is described herein. In one example, a dopant concentration within a top cladding material is between 3-6% (wt.). Given a tuned top cladding composition, a width of the waveguide core is pre-selected such that birefringence is minimized, i.e., a zero, or near zero. The desirable width of the waveguide core is determined by calculating the distribution of stress in the top cladding over a change in temperature. From this distribution of stress, a relationship between the polarization dependent wavelength and variable widths of the waveguide in the arrayed waveguide grating are determined. This relationship determines a zero value, or near zero value, of polarization dependent wavelength for a given range of waveguide widths. Accordingly, the width of the waveguide may be selected such that the polarization dependent wavelength is minimized.

    摘要翻译: 本文描述了通过选择用于调谐顶部包层的波导芯宽度来控制波导双折射的方法和装置。 在一个实例中,顶部包层材料内的掺杂剂浓度在3-6%(重量)之间。 给定一个调整的顶部包层组成,预先选择波导芯的宽度,使得双折射最小化,即零或接近零。 通过计算在顶部包层中的应力在温度变化中的分布来确定波导芯的期望宽度。 根据这种应力分布,确定阵列波导光栅中波导的偏振相关波长与可变宽度之间的关系。 对于给定的波导宽度范围,该关系确定偏振相关波长的零值或近零值。 因此,可以选择波导的宽度使得偏振相关波长最小化。

    Top cap process for reducing polarization dependent wavelength shift in planar lightwave circuits
    4.
    发明授权
    Top cap process for reducing polarization dependent wavelength shift in planar lightwave circuits 有权
    用于减小平面光波电路中的偏振相关波长偏移的顶盖工艺

    公开(公告)号:US06826345B1

    公开(公告)日:2004-11-30

    申请号:US10165903

    申请日:2002-06-10

    IPC分类号: G02B610

    CPC分类号: G02B6/126 G02B2006/121

    摘要: One aspect of the invention relates to a PLC containing at least one waveguide on a bottom clad layer, each waveguide having a top cap layer on an upper surface thereof, and a top clad layer over the waveguides having the top cap on the upper portion thereof. The presence of the top cap reduces waveguide birefringence and resultant polarization dependence in PLCs, particularly for reducing polarization dependent wavelength shift in AWGs. Another aspect of the invention relates to methods of making PLCs involving forming a waveguide layer on a bottom clad layer, forming a top cap layer on the waveguide layer, patterning the waveguide layer and the top cap layer using a mask to form waveguides having a top cap on an upper portion thereof, and forming a top clad layer over the waveguides having the top cap on the upper portion thereof.

    摘要翻译: 本发明的一个方面涉及一种在底部包层上含有至少一个波导的PLC,每个波导在其上表面上具有顶盖层,并且在该波导上方的顶部覆盖层在其上部具有顶盖 。 顶盖的存在降低了PLC中的波导双折射和合成极化依赖性,特别是为了减少AWG中的偏振相关波长偏移。 本发明的另一方面涉及制造PLC的方法,其涉及在底部包层上形成波导层,在波导层上形成顶盖层,使用掩模对波导层和顶盖层进行图案化以形成具有顶部的波导 盖在其上部,并且在其上部具有顶盖的波导上形成顶部包层。

    Reducing polarization dependent loss caused by polarization dependent wavelength shift using core over-etch for planar lightwave circuit fabrication

    公开(公告)号:US06542687B2

    公开(公告)日:2003-04-01

    申请号:US09873068

    申请日:2001-05-31

    IPC分类号: G02B610

    摘要: A method of making a polarization insensitive optical waveguide structure. An optical core layer is formed on a substrate, wherein the optical core layer has a higher refractive index than the substrate. A mask is formed over the optical core layer. The unmasked areas of the optical core layer are then over-etched to define the core, wherein the over-etching removes the unmasked area of the optical core layer and a portion of the substrate disposed beneath the unmasked area, and defines the optical core. The mask is subsequently removed from the optical core. A cladding layer is then formed over the optical core and the substrate, the cladding layer having a lower refractive index than the optical core, to form a polarization insensitive optical waveguide structure. The amount of over-etching can be controlled to control an amount of substrate disposed beneath the unmasked area of the optical core layer that is removed. The amount of substrate removed, in turn, controls the polarization sensitivity of the optical waveguide structure. The amount of the portion of the substrate removed during the over-etching can be determined to minimize the polarization dependent wavelength shift and the polarization dependent loss of the optical waveguide structure. The amount of the portion of the substrate removed during the over-etching can be determined in accordance with a blanket stress of the cladding layer. The over-etching can be within a range between 7.5 percent and 30 percent.

    INACTIVE DUMMY PIXELS
    6.
    发明申请
    INACTIVE DUMMY PIXELS 有权
    不活泼的像素

    公开(公告)号:US20120236009A1

    公开(公告)日:2012-09-20

    申请号:US13329502

    申请日:2011-12-19

    IPC分类号: G09G5/00 H01L33/08 G06T1/00

    CPC分类号: G02B26/001

    摘要: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for a display with inactive dummy pixels. A display apparatus may include subpixels having a first electrode layer and a second electrode layer. The first electrode layer of an edge subpixel may include an opening, which may be made large enough to prevent the edge subpixel from actuating. The size of the openings also may be selected to attain a desired overall reflectivity for an array of edge subpixels. For example, the size of the openings may be selected to make the reflectivity of an edge pixel array similar to the reflectivity of a routing area.

    摘要翻译: 本公开提供了系统,方法和装置,包括在计算机存储介质上编码的计算机程序,用于具有非活动虚拟像素的显示器。 显示装置可以包括具有第一电极层和第二电极层的子像素。 边缘子像素的第一电极层可以包括开口,其可以被制成足够大以防止边缘子像素致动。 可以选择开口的尺寸以获得边缘子像素阵列的期望的总体反射率。 例如,可以选择开口的尺寸以使边缘像素阵列的反射率类似于布线区域的反射率。

    Seal ring for preventing crack propagation in integrated circuit devices
    7.
    发明授权
    Seal ring for preventing crack propagation in integrated circuit devices 有权
    用于防止集成电路器件中的裂纹扩展的密封环

    公开(公告)号:US08093719B1

    公开(公告)日:2012-01-10

    申请号:US11281098

    申请日:2005-11-16

    申请人: Farnaz Parhami

    发明人: Farnaz Parhami

    IPC分类号: H01L23/04

    摘要: In one embodiment, an integrated circuit device includes an active area encompassed by a seal ring. The seal ring may include a deep moat formed on an outer edge of the seal ring. The deep moat may have a depth that extends substantially to the substrate to prevent cracks from propagating into the active area. Alternatively or in addition, the seal ring may include redundant vias.

    摘要翻译: 在一个实施例中,集成电路器件包括由密封环包围的有源区域。 密封环可以包括形成在密封环的外边缘上的深沟槽。 深沟槽可以具有基本上延伸到基底的深度,以防止裂纹传播到有源区域。 或者或另外,密封环可以包括冗余的通孔。

    Method and system for reducing dn/dt birefringence in a thermo-optic PLC device
    8.
    发明授权
    Method and system for reducing dn/dt birefringence in a thermo-optic PLC device 有权
    用于降低热光PLC设备中dn / dt双折射的方法和系统

    公开(公告)号:US06704487B2

    公开(公告)日:2004-03-09

    申请号:US09927256

    申请日:2001-08-10

    IPC分类号: G02B610

    摘要: A method of making an optical waveguide structure for an active PLC device having a reduced dn/dt birefringence. The method includes the step of forming a waveguide core layer on a bottom cladding, the waveguide core layer having a higher refractive index than the bottom cladding. The waveguide core layer is then etched to define a waveguide core. A top cladding is subsequently formed over the waveguide core and the bottom cladding. The top cladding also has a lower refractive index than the waveguide core. The top cladding is then etched to define a first trench and a second trench parallel to the waveguide core. The first trench and the second trench are configured to relieve a stress on the waveguide core. This stress can be induced by a heater, as in a case where the active PLC is a thermo-optic PLC. The first trench and the second trench can extend from an upper surface of the top cladding to an upper surface of the bottom cladding. The first trench and the second trench can extend from the upper surface of the top cladding into a portion of the underlying substrate. The first trench and the second trench are configured to balance a tensile stress within the waveguide core. A cap can be formed over the waveguide core prior to forming the top cladding to further balance the tensile stress within the waveguide core. The bottom cladding can have a higher dopant concentration than the top cladding.

    摘要翻译: 一种制造具有减小的dn / dt双折射的有源PLC器件的光波导结构的方法。 该方法包括在底部包层上形成波导芯层的步骤,该波导芯层具有比底部包层更高的折射率。 然后蚀刻波导芯层以限定波导芯。 随后在波导芯和底部包层上形成顶部覆层。 顶部覆层也具有比波导芯更低的折射率。 然后蚀刻顶部覆层以限定平行于波导芯的第一沟槽和第二沟槽。 第一沟槽和第二沟槽构造成缓解波导芯上的应力。 这种应力可以由加热器引起,如在活动PLC是热光PLC的情况下。 第一沟槽和第二沟槽可以从顶部包层的上表面延伸到底部包层的上表面。 第一沟槽和第二沟槽可以从顶部包层的上表面延伸到下面的衬底的一部分中。 第一沟槽和第二沟槽构造成平衡波导芯内的拉伸应力。 在形成顶部包层之前,可以在波导芯上方形成盖,以进一步平衡波导芯内的拉伸应力。 底部包层可以具有比顶部包层更高的掺杂剂浓度。

    Inactive dummy pixels
    9.
    发明授权
    Inactive dummy pixels 有权
    非活动虚拟像素

    公开(公告)号:US08988440B2

    公开(公告)日:2015-03-24

    申请号:US13329502

    申请日:2011-12-19

    CPC分类号: G02B26/001

    摘要: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for a display with inactive dummy pixels. A display apparatus may include subpixels having a first electrode layer and a second electrode layer. The first electrode layer of an edge subpixel may include an opening, which may be made large enough to prevent the edge subpixel from actuating. The size of the openings also may be selected to attain a desired overall reflectivity for an array of edge subpixels. For example, the size of the openings may be selected to make the reflectivity of an edge pixel array similar to the reflectivity of a routing area.

    摘要翻译: 本公开提供了系统,方法和装置,包括在计算机存储介质上编码的计算机程序,用于具有非活动虚拟像素的显示器。 显示装置可以包括具有第一电极层和第二电极层的子像素。 边缘子像素的第一电极层可以包括开口,其可以被制成足够大以防止边缘子像素致动。 可以选择开口的尺寸以获得边缘子像素阵列的期望的总体反射率。 例如,可以选择开口的尺寸以使边缘像素阵列的反射率类似于布线区域的反射率。

    SYSTEM AND METHOD FOR TUNING MULTI-COLOR DISPLAYS
    10.
    发明申请
    SYSTEM AND METHOD FOR TUNING MULTI-COLOR DISPLAYS 审中-公开
    用于调谐多色显示的系统和方法

    公开(公告)号:US20120274666A1

    公开(公告)日:2012-11-01

    申请号:US13279161

    申请日:2011-10-21

    IPC分类号: G09G5/10

    摘要: This disclosure provides systems, methods and apparatuses, including computer programs encoded on computer-readable storage media, for calibrating a display. In one aspect, a method of calibrating a display includes determining one or more array voltages and, based on the determined array voltages, determining one or more drive scheme voltages. The determined drive scheme voltages may include, for example, a single segment voltage applied to all of the display elements of the array, and multiple common voltages applies to multiple subsets of the display elements of the array.

    摘要翻译: 本公开提供了用于校准显示器的系统,方法和装置,包括在计算机可读存储介质上编码的计算机程序。 一方面,校准显示器的方法包括确定一个或多个阵列电压,并且基于所确定的阵列电压来确定一个或多个驱动方案电压。 所确定的驱动方案电压可以包括例如施加到阵列的所有显示元件的单个段电压,并且多个公共电压适用于阵列的显示元件的多个子集。