公开(公告)号：US20060268618A1

公开(公告)日：2006-11-30

申请号：US11462920

申请日：2006-08-07

申请人： Farookh Moogat ,  Yan Li ,  Alexander Mak

发明人： Farookh Moogat ,  Yan Li ,  Alexander Mak

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/30

摘要： In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

摘要翻译： 在非易失性存储器系统中，当发现由用于编程存储器单元的电荷泵提供的电压泵浦脉冲与参考电压不匹配时，电压泵浦脉冲的编程时间周期被调整为保持的值 基本上没有变化，直到编程周期结束。 以这种方式，编程脉冲的有效编程时间段的波动在编程周期的其余部分被阻止，使得阈值电压分布的加宽不会发生或将被减少。 该特征允许为编程脉冲指定短的编程时间段以提高性能，同时允许当电荷泵在导致其缓慢和/或弱的条件下运行时增加编程时间段的灵活性。

公开(公告)号：US20060018160A1

公开(公告)日：2006-01-26

申请号：US10896096

申请日：2004-07-20

申请人： Farookh Moogat ,  Yan Li ,  Alexander Mak

发明人： Farookh Moogat ,  Yan Li ,  Alexander Mak

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/30

摘要： In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

摘要翻译： 在非易失性存储器系统中，当发现由用于编程存储器单元的电荷泵提供的电压泵浦脉冲与参考电压不匹配时，电压泵浦脉冲的编程时间周期被调整为保持的值 基本上没有变化，直到编程周期结束。 以这种方式，编程脉冲的有效编程时间段的波动在编程周期的其余部分被阻止，使得阈值电压分布的加宽不会发生或将被减少。 该特征允许为编程脉冲指定短的编程时间段以提高性能，同时允许当电荷泵在导致其缓慢和/或弱的条件下运行时增加编程时间段的灵活性。

公开(公告)号：US07450426B2

公开(公告)日：2008-11-11

申请号：US11548267

申请日：2006-10-10

申请人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

发明人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3481

摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

摘要翻译： 与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。 当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。 施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。 在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。 在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程，在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，增量值可以增加 同时页面。

公开(公告)号：US20080084752A1

公开(公告)日：2008-04-10

申请号：US11548267

申请日：2006-10-10

申请人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

发明人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3481

摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

摘要翻译： 与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。 当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。 施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。 在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。 在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程，在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，增量值可以增加 同时页面。

公开(公告)号：US07313023B2

公开(公告)日：2007-12-25

申请号：US11078173

申请日：2005-03-11

申请人： Yan Li ,  Farookh Moogat

发明人： Yan Li ,  Farookh Moogat

IPC分类号： G11C7/18 ,  G11C8/12 ,  G11C7/02

CPC分类号： G11C7/18 ,  G11C16/0483 ,  G11C16/24 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit lines and a bottom set of sense amps control the odd bit lines. The segmentation transistors turn on or off depending on the selected word line location in the array. Since bit line capacitance is mainly from the metal bit line to bit line coupling to their immediate neighbors, the bit line neighbors in the partitioned array are floating in some segments of the bit lines. The overall bit line capacitance is significantly reduced with a negligible increase in die size, resulting in reduced sensing times and enhanced read and write performance.

摘要翻译： 通过可切换地划分阵列中的位线来分割N个段中的存储器阵列的本发明。 在示例性实施例中，顶部的一组感测放大器控制偶数位线，并且底部的一组感测放大器控制奇数位线。 根据阵列中选定的字线位置，分割晶体管导通或关断。 由于位线电容主要是从金属位线到位线耦合到它们的直接邻居，所以分割阵列中的位线相邻部分浮动在位线的某些段中。 总体位线电容显着降低，管芯尺寸增加可以忽略不计，从而减少了传感时间，提高了读写性能。

公开(公告)号：US07474561B2

公开(公告)日：2009-01-06

申请号：US11548264

申请日：2006-10-10

申请人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

发明人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3481

摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

摘要翻译： 与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。 当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。 施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。 在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。 在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程，在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，增量值可以增加 同时页面。

公开(公告)号：US20060203587A1

公开(公告)日：2006-09-14

申请号：US11078173

申请日：2005-03-11

申请人： Yan Li ,  Farookh Moogat

发明人： Yan Li ,  Farookh Moogat

IPC分类号： G11C7/02

CPC分类号： G11C7/18 ,  G11C16/0483 ,  G11C16/24 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit lines and a bottom set of sense amps control the odd bit lines. The segmentation transistors turn on or off depending on the selected word line location in the array. Since bit line capacitance is mainly from the metal bit line to bit line coupling to their immediate neighbors, the bit line neighbors in the partitioned array are floating in some segments of the bit lines. The overall bit line capacitance is significantly reduced with a negligible increase in die size, resulting in reduced sensing times and enhanced read and write performance.

摘要翻译： 通过可切换地划分阵列中的位线来分割N个段中的存储器阵列的本发明。 在示例性实施例中，顶部的一组感测放大器控制偶数位线，并且底部的一组感测放大器控制奇数位线。 根据阵列中选定的字线位置，分割晶体管导通或关断。 由于位线电容主要是从金属位线到位线耦合到它们的直接邻居，所以分割阵列中的位线相邻部分浮动在位线的某些段中。 总体位线电容显着降低，管芯尺寸增加可以忽略不计，从而减少了传感时间，提高了读写性能。

公开(公告)号：US07110298B2

公开(公告)日：2006-09-19

申请号：US10896096

申请日：2004-07-20

申请人： Farookh Moogat ,  Yan Li ,  Alexander K. Mak

发明人： Farookh Moogat ,  Yan Li ,  Alexander K. Mak

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/30

摘要： In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

摘要翻译： 在非易失性存储器系统中，当发现由用于编程存储器单元的电荷泵提供的电压泵浦脉冲与参考电压不匹配时，电压泵浦脉冲的编程时间周期被调整为保持的值 基本上没有变化，直到编程周期结束。 以这种方式，编程脉冲的有效编程时间段的波动在编程周期的其余部分被阻止，使得阈值电压分布的加宽不会发生或将被减少。 该特征允许为编程脉冲指定短的编程时间段以提高性能，同时允许当电荷泵在导致其缓慢和/或弱的条件下运行时增加编程时间段的灵活性。

公开(公告)号：US20080084751A1

公开(公告)日：2008-04-10

申请号：US11548264

申请日：2006-10-10

申请人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

发明人： Yan Li ,  Fanglin Zhang ,  Toru Miwa ,  Farookh Moogat

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3481

摘要： The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

摘要翻译： 与其他状态相比，多状态非易失性闪存器件中的最低编程状态可能会受到位线到位线电容电荷耦合的增加的影响。 当将存储器单元编程到最低可编程状态时，可以使用较小的值将增加的电压脉冲施加到存储单元的编程电压递增。 施加电压的较小增量允许更高的精度和更窄的阈值电压分布，以补偿编程到该状态的单元所经历的不成比例的电荷耦合。 在一些实现中从较低页切换到上页编程时，可以使用较小的增量值。 在流水线编程架构中，形成物理页面的单元存储两个逻辑页面的数据和一个逻辑页面的编程在接收另一个逻辑页面的数据之前开始，当从第一个逻辑页面的编程切换到编程时，可以增加增量值 同时页面。

公开(公告)号：US07262998B2

公开(公告)日：2007-08-28

申请号：US11462920

申请日：2006-08-07

申请人： Farookh Moogat ,  Yan Li ,  Alexander K. Mak

发明人： Farookh Moogat ,  Yan Li ,  Alexander K. Mak

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/30

摘要： In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

摘要翻译： 在非易失性存储器系统中，当发现由用于编程存储器单元的电荷泵提供的电压泵浦脉冲与参考电压不匹配时，电压泵浦脉冲的编程时间周期被调整为保持的值 基本上没有变化，直到编程周期结束。 以这种方式，编程脉冲的有效编程时间段的波动在编程周期的其余部分被阻止，使得阈值电压分布的加宽不会发生或将被减少。 该特征允许为编程脉冲指定短的编程时间段以提高性能，同时允许当电荷泵在导致其缓慢和/或弱的条件下运行时增加编程时间段的灵活性。