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1.发明授权公开(公告)号：US07823106B2
公开(公告)日：2010-10-26
申请号：US12045984
申请日：2008-03-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.
摘要翻译： 一种方法，计算机系统和程序产品引入了将可变性能排名参数添加到电路图中，以驱动实现改进的效果，提高效率，提升性能或性能中立。 该信息配对，以便在芯片上实现的电路设计中完成更完整的可制造性修改设计。 在这个问题上，产量和芯片性能均有所提高。
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2.发明申请公开(公告)号：US20090235214A1
公开(公告)日：2009-09-17
申请号：US12045984
申请日：2008-03-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.
摘要翻译： 一种方法，计算机系统和程序产品引入了将可变性能排名参数添加到电路图中，以驱动实现改进的效果，提高效率，提升性能或性能中立。 该信息配对，以便在芯片上实现的电路设计中完成更完整的可制造性修改设计。 在这个问题上，产量和芯片性能均有所提高。
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公开(公告)号：US07707522B2
公开(公告)日：2010-04-27
申请号：US11939761
申请日：2007-11-14
申请人： Mark R. Beckenbaugh , Michael D. Cesky , Jay A. Lawrence , Lily L. Wang , Nicholas G. Young , John W. Zack , Laura M. Zumbrunnen
发明人： Mark R. Beckenbaugh , Michael D. Cesky , Jay A. Lawrence , Lily L. Wang , Nicholas G. Young , John W. Zack , Laura M. Zumbrunnen
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected.
摘要翻译： 在将线路布线到集成电路中的形状以最小化掩模处理期间不期望的点动创建的方法中，导线相对于导线连接到该形状的形状的选定边缘的多个可能的放置是 决心。 为每个展示位置分配成本，成本指示将在对应于展示位置的屏蔽过程中创建的点动量，其中更大的成本表示在掩蔽过程中将产生比由 安置费用较低。 选择具有多个可能的展示位置的最低成本的展示位置。
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公开(公告)号：US07530041B1
公开(公告)日：2009-05-05
申请号：US12124119
申请日：2008-05-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a width difference between a width of the wire and a width of the source, and dividing the width difference by the width of the wire; and modifying a size of the wire if the first size differential is less than a maximum width percentage and if a length of the source is less than a length range specified by a user.
摘要翻译： 一种用于自动线尺寸修改的方法，包括将导线路由到源的步骤; 通过计算所述线的宽度与所述源的宽度之间的宽度差，并且将所述宽度差除以所述线的宽度，来检测所述线和所述源之间的第一尺寸差分; 以及如果所述第一尺寸差异小于最大宽度百分比并且如果所述源的长度小于由用户指定的长度范围，则修改所述电线的尺寸。
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公开(公告)号：US20090125860A1
公开(公告)日：2009-05-14
申请号：US11939761
申请日：2007-11-14
申请人： Mark R. Beckenbaugh , Michael D. Cesky , Jay A. Lawrence , Lily L. Wang , Nicholas G. Young , John W. Zack , Laura M. Zumbrunnen
发明人： Mark R. Beckenbaugh , Michael D. Cesky , Jay A. Lawrence , Lily L. Wang , Nicholas G. Young , John W. Zack , Laura M. Zumbrunnen
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected.
摘要翻译： 在将线路布线到集成电路中的形状以最小化掩模处理期间不期望的点动创建的方法中，导线相对于导线连接到该形状的形状的选定边缘的多个可能的放置是 决心。 为每个展示位置分配成本，成本指示将在对应于展示位置的屏蔽过程中创建的点动量，其中更大的成本表示在掩蔽过程中将产生比由 安置费用较低。 选择具有多个可能的展示位置的最低成本的展示位置。
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公开(公告)号：US07530042B1
公开(公告)日：2009-05-05
申请号：US12124120
申请日：2008-05-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a first width difference between a length of the wire and a width of the source, and dividing the first width difference by the width of the source; detecting a second size differential between the wire and the source if the first size differential is less than a maximum length percentage by calculating a second width difference between the width of the source and a width of the wire, and dividing the second width difference by the width of the source; and modifying a size of the wire if the second size differential is less than a maximum width percentage.
摘要翻译： 一种用于自动线尺寸修改的方法，包括将导线路由到源的步骤; 通过计算所述线的长度和所述源的宽度之间的第一宽度差，并且将所述第一宽度差除以所述源的宽度来检测所述线和所述源之间的第一尺寸差分; 如果所述第一尺寸差异小于最大长度百分比，则通过计算所述源的宽度和所述线的宽度之间的第二宽度差，并且将所述第二宽度差除以所述第一宽度差， 源的宽度; 以及如果所述第二尺寸差小于最大宽度百分比，则修改所述电线的尺寸。
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公开(公告)号：US20090045840A1
公开(公告)日：2009-02-19
申请号：US11838273
申请日：2007-08-14
IPC分类号： H03K19/0948
CPC分类号： H03K19/00338
摘要： A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.
摘要翻译： 用于诸如专用集成电路（ASIC）的可编程器件的逻辑书通过在不同的阱区域中提供相同掺杂类型的晶体管来实现改善的辐射耐受性，该晶体管通过具有互补掺杂的介入阱区物理隔离。 例如，n型场效应晶体管（NFET）可以位于具有单独的P阱区域的书的两个外排中，而p型晶体管位于本书的两个内部行中，共享共同的Nwell区。 由于在单独的阱中的NFET在物理上彼此隔离，所以在两个外部行中使用两个NFET的电路结构不太可能遭受单次辐射冲击的多次故障。 本发明的更复杂的实施例包括具有隔离的N沟槽和孔的堆叠中的附加晶体管行。
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公开(公告)号：US07725870B2
公开(公告)日：2010-05-25
申请号：US11838286
申请日：2007-08-14
CPC分类号： H01L21/823892 , G06F17/5072 , H01L27/0203 , H01L27/0207 , H01L27/092 , H01L27/11807
摘要： A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.
摘要翻译： 用于诸如专用集成电路（ASIC）的可编程器件的逻辑书通过在相邻晶体管之间的植入物井中提供凹口来实现改善的辐射耐受性，并且用作为电荷迁移的屏障的互补阱区填充凹口。 例如，一排n型场效应晶体管（NFET）位于P阱区域中，而一排p型晶体管位于Nwell区域中，N阱区域的部分在NFET之间延伸。 本发明的更复杂的实施例包括嵌入井岛，以为本书的两行中的相邻晶体管提供障碍。
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公开(公告)号：US07698681B2
公开(公告)日：2010-04-13
申请号：US11838273
申请日：2007-08-14
IPC分类号： G06F17/50 , H03K19/00 , H03K19/177 , H01L27/088
CPC分类号： H03K19/00338
摘要： A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.
摘要翻译： 用于诸如专用集成电路（ASIC）的可编程器件的逻辑书通过在不同的阱区域中提供相同掺杂类型的晶体管来实现改善的辐射耐受性，该晶体管通过具有互补掺杂的介入阱区物理隔离。 例如，n型场效应晶体管（NFET）可以位于具有单独的P阱区域的书的两个外排中，而p型晶体管位于本书的两个内部行中，共享共同的Nwell区。 由于在单独的阱中的NFET在物理上彼此隔离，所以在两个外部行中使用两个NFET的电路结构不太可能遭受单次辐射冲击的多次故障。 本发明的更复杂的实施例包括具有隔离的N沟槽和孔的堆叠中的附加晶体管行。
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公开(公告)号：US20090077518A1
公开(公告)日：2009-03-19
申请号：US11856819
申请日：2007-09-18
申请人： Mark R. Beckenbaugh , Michael D. Cesky , Jay A. Lawrence , Lily L. Wang , Nicholas G. Young , John W. Zack
发明人： Mark R. Beckenbaugh , Michael D. Cesky , Jay A. Lawrence , Lily L. Wang , Nicholas G. Young , John W. Zack
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer program product stored on machine readable media includes machine executable instructions for displaying a layout of a circuit design, the product including instructions for: over a plurality of layers within a design, identifying at least one of a derived level and a device defined within the plurality; and displaying the at least one derived level and device to a user.
摘要翻译： 存储在机器可读介质上的计算机程序产品包括用于显示电路设计的布局的机器可执行指令，该产品包括用于：在设计内的多个层上的指令，以识别导出级别和在 多个; 以及将至少一个派生级别和设备显示给用户。
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