公开(公告)号：US07569883B2

公开(公告)日：2009-08-04

申请号：US11285759

申请日：2005-11-21

申请人： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri ,  Antonio Giuseppe Grimaldi ,  Gaetano Bazzano

发明人： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri ,  Antonio Giuseppe Grimaldi ,  Gaetano Bazzano

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/4983

摘要： Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.

摘要翻译： 这种类型的功率电子MOS器件包括多个基本功率MOS晶体管和一个栅极结构，该栅极结构包括由第一导电材料（例如多晶硅），多个栅极指状物或连接到栅极焊盘的金属轨道 至少一个与至少一个所述导电带串联布置的连接层。 这种门结构包括形成在导电条的上表面上并适当地形成在连接层上的至少多个独立的岛。 所述岛通过至少一种第二导电材料如硅化物实现。

公开(公告)号：US20060220121A1

公开(公告)日：2006-10-05

申请号：US11285759

申请日：2005-11-21

申请人： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri ,  Antonio Grimaldi ,  Gaetano Bazzano

发明人： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri ,  Antonio Grimaldi ,  Gaetano Bazzano

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/4983

摘要： Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.

公开(公告)号：US07304335B2

公开(公告)日：2007-12-04

申请号：US11279967

申请日：2006-04-17

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L29/78 ,  H01L29/10

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712

摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

摘要翻译： 具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。 栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。 第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

公开(公告)号：US07067363B2

公开(公告)日：2006-06-27

申请号：US10749134

申请日：2003-12-30

申请人： Angelo Magri′ ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

发明人： Angelo Magri′ ,  Ferruccio Frisina ,  Giuseppe Ferla ,  Marco Camalleri

IPC分类号： H01L21/337 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712

摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

摘要翻译： 具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。 栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。 第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

公开(公告)号：US20110081759A1

公开(公告)日：2011-04-07

申请号：US12967845

申请日：2010-12-14

申请人： Angelo Magri ,  Ferruccio Frisina ,  Giuseppe Ferla

发明人： Angelo Magri ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L21/8232

CPC分类号： H01L29/7802 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/4983

摘要： Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

公开(公告)号：US06468866B2

公开(公告)日：2002-10-22

申请号：US09427237

申请日：1999-10-26

申请人： Ferruccio Frisina ,  Angelo Magri ,  Giuseppe Ferla ,  Richard A. Blanchard

发明人： Ferruccio Frisina ,  Angelo Magri ,  Giuseppe Ferla ,  Richard A. Blanchard

IPC分类号： H01L21336

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66333

摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

摘要翻译： MOS技术功率器件包括第一导电类型的半导体材料层，覆盖半导体材料层的导电绝缘栅极层和多个基本功能单元。 导电绝缘栅层包括置于半导体材料层上方的第一绝缘材料层，位于第一绝缘材料层上方的导电材料层和置于导电材料层上方的第二绝缘材料层。 每个基本功能单元包括形成在半导体材料层中的第二导电类型的细长体区域。 每个基本功能单元还包括在细长体区域上方延伸的绝缘栅极层中的细长窗口。 每个细长体区域包括掺杂有第一导电类型的掺杂剂的源区，插入有细长体区的一部分，其中不提供第一导电类型的掺杂剂。 MOS技术功率器件还包括多个绝缘材料侧壁间隔物，其沿着每个细长窗口的细长边缘设置在半导体材料层之上，以密封绝缘栅极层中每个细长窗口的边缘与设置在绝缘栅极上的源极金属层 层和半导体材料层。 源极金属层沿着细长主体区域的长度通过每个细长窗口接触每个体区域和每个源极区域。

公开(公告)号：US6064087A

公开(公告)日：2000-05-16

申请号：US739466

申请日：1996-10-29

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L29/74 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/749 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66333 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/0847

摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

公开(公告)号：US07875936B2

公开(公告)日：2011-01-25

申请号：US11285741

申请日：2005-11-21

申请人： Angelo Magri ,  Ferruccio Frisina ,  Giuseppe Ferla

发明人： Angelo Magri ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L27/088

CPC分类号： H01L29/7802 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/4983

摘要： Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

摘要翻译： 该功率MOS器件包括具有相应栅极结构的多个基本功率MOS晶体管，并且包括具有厚度中心部分和厚度减小的侧部的双重厚度的栅极氧化物。 这种具有栅极结构的器件包括第一栅极导电部分，该第一栅极导电部分重叠在所述减小厚度的横向部分上，以便为基本MOS晶体管限定栅电极以及导电结构或网状物。 这种导电结构包括多个第二导电部分，其重叠在栅极氧化物的厚的中心部分上并且通过多个导电桥彼此互连并连接到第一栅极导电部分。

公开(公告)号：US06566690B2

公开(公告)日：2003-05-20

申请号：US09427236

申请日：1999-10-26

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L2974

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66333

摘要： A MOS technology power device includes a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

摘要翻译： MOS技术功率器件包括第一导电类型的半导体材料层，覆盖半导体材料层的导电绝缘栅极层和多个基本功能单元。 导电绝缘栅层包括置于半导体材料层上方的第一绝缘材料层，位于第一绝缘材料层上方的导电材料层和置于导电材料层上方的第二绝缘材料层。 每个基本功能单元包括形成在半导体材料层中的第二导电类型的细长体区域。 每个基本功能单元还包括在细长体区域上方延伸的绝缘栅极层中的细长窗口。 每个细长体区域包括掺杂有第一导电类型的掺杂剂的源区，插入有细长体区的一部分，其中不提供第一导电类型的掺杂剂。 MOS技术功率器件还包括多个绝缘材料侧壁间隔物，其沿着每个细长窗口的细长边缘设置在半导体材料层之上，以密封绝缘栅极层中每个细长窗口的边缘与设置在绝缘栅极上的源极金属层 层和半导体材料层。 源极金属层沿着细长主体区域的长度通过每个细长窗口接触每个体区域和每个源极区域。

公开(公告)号：US06548864B2

公开(公告)日：2003-04-15

申请号：US09426510

申请日：1999-10-26

申请人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

发明人： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC分类号： H01L2994

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66712

摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window. The second insulating material layer includes a second elongated window extending above each elongated body region. The second insulating material layer seals the edges of the conductive material layer from a source metal layer disposed over the second insulating material layer. The source metal layer contacts each body region and each source region through each second elongated window along the length of the elongated body region.

摘要翻译： MOS技术功率器件包括第一导电类型的半导体材料层，多个基本功能单元，放置在半导体材料层上方的第一绝缘材料层和放置在第一绝缘材料层上方的导电材料层。 每个基本功能单元包括形成在半导体材料层中的第二导电类型的细长体区域。 每个基本功能单元还包括在细长主体区域上方延伸的导电材料层中的第一细长窗口。 每个细长体区域包括掺杂有第一导电类型的掺杂剂的源区，插入有细长体区的一部分，其中不提供第一导电类型的掺杂剂。 MOS技术功率器件还包括设置在导电材料层上方并沿着第一细长窗的细长边缘设置的第二绝缘材料层。 第二绝缘材料层包括在每个细长体区域之上延伸的第二细长窗口。 第二绝缘材料层将导电材料层的边缘与设置在第二绝缘材料层上的源极金属层密封。 源金属层沿着细长主体区域的长度通过每个第二细长窗口接触每个体区域和每个源区域。