公开(公告)号：US20090160015A1

公开(公告)日：2009-06-25

申请号：US11961410

申请日：2007-12-20

申请人： Florin UDREA ,  Gehan Anil Joseph Amaratunga ,  Tanya Trajkovic ,  Vasantha Pathirana

发明人： Florin UDREA ,  Gehan Anil Joseph Amaratunga ,  Tanya Trajkovic ,  Vasantha Pathirana

IPC分类号： H01L29/06 ,  H01L21/306

CPC分类号： H01L29/0657 ,  H01L21/8249 ,  H01L22/26 ,  H01L29/063 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/7393 ,  H01L29/7816

摘要： In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.

摘要翻译： 在功率半导体器件和形成功率半导体器件的方法中，将半导体衬底的薄层留在半导体器件的漂移区域的下方。 功率半导体器件具有包括漂移区的有源区，并且具有形成在设置在半导体衬底上的层中的顶表面和底表面。 在有源区下面的半导体衬底的一部分被去除以在漂移区下方留下半导体衬底的薄层。 电端子直接或间接提供到有源区的顶表面，以允许电压横向跨越漂移区域施加。

公开(公告)号：US20100032712A1

公开(公告)日：2010-02-11

申请号：US12186231

申请日：2008-08-05

申请人： Florin UDREA ,  Vasantha PATHIRANA ,  Tanya TRAJKOVIC ,  Nishad UDUGAMPOLA

发明人： Florin UDREA ,  Vasantha PATHIRANA ,  Tanya TRAJKOVIC ,  Nishad UDUGAMPOLA

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0839 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7394 ,  H01L29/7824

摘要： A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.

摘要翻译： 功率半导体器件具有顶表面和相对的底表面，其下面的一部分是半导体衬底的厚部分。 装置的漂移区域的至少一部分具有没有或仅有半导体衬底的薄的部分位于其下方。 顶表面具有高电压端子和与其连接的低电压端子，以允许跨越漂移区域横向施加电压。 在顶表面上设置至少两个MOS（金属氧化物半导体）栅极。 器件在其顶表面处具有至少一个相对高度掺杂的区域，其在所述第一和第二MOS栅极之间延伸并与之接触。 该器件具有改进的防止寄生晶体管触发或闩锁的保护，而不会导致导通电压降或开关速度受损。

公开(公告)号：US20090058498A1

公开(公告)日：2009-03-05

申请号：US11847234

申请日：2007-08-29

申请人： Florin UDREA ,  Nishad Udugampola ,  Gehan Anil Joseph Amaratunga

发明人： Florin UDREA ,  Nishad Udugampola ,  Gehan Anil Joseph Amaratunga

IPC分类号： H03K17/56 ,  H03K17/74

CPC分类号： H03K17/567 ,  H01L29/0638 ,  H01L29/7393 ,  H03K17/08142 ,  H03K17/6871 ,  H03K2017/6878

摘要： A half bridge circuit has a first switch having at least one control gate and a second switch having at least two control gates. A first driver has an output connected to a control gate of the first switch. A second driver has an output connected to a first control gate of the second switch. The output of the first driver is connected to a second control gate of the second switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first switch, a positive voltage is applied to the second control gate of the second switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first switch, a negative voltage is applied to said second control gate of the second switch.

摘要翻译： 半桥电路具有具有至少一个控制栅极的第一开关和具有至少两个控制栅极的第二开关。 第一驱动器具有连接到第一开关的控制栅极的输出端。 第二驱动器具有连接到第二开关的第一控制栅极的输出。 第一驱动器的输出通过电路装置连接到第二开关的第二控制栅极，使得当第一驱动器被操作以向第一开关的控制栅极施加高正正电压时，施加正电压 并且使得当第一驱动器被操作以向第一开关的控制栅极施加低，零或小的电压时，负电压被施加到第二开关的第二控制栅极的第二控制栅极 开关。

公开(公告)号：US20110254177A1

公开(公告)日：2011-10-20

申请号：US13171788

申请日：2011-06-29

申请人： Rajesh Kumar MALHAN ,  C Mark JOHNSON ,  Cyril BUTTAY ,  Jeremy RASHID ,  Florin UDREA

发明人： Rajesh Kumar MALHAN ,  C Mark JOHNSON ,  Cyril BUTTAY ,  Jeremy RASHID ,  Florin UDREA

IPC分类号： H01L23/48

CPC分类号： H01L23/49844 ,  H01L23/5385 ,  H01L24/31 ,  H01L24/83 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/33 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

摘要翻译： 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。

公开(公告)号：US20120267532A1

公开(公告)日：2012-10-25

申请号：US13466626

申请日：2012-05-08

申请人： Florin UDREA ,  Julian GARDNER ,  Syed Zeeshan ALI ,  Mohamed Foysol CHOWDHURY ,  Ilie POENARU

发明人： Florin UDREA ,  Julian GARDNER ,  Syed Zeeshan ALI ,  Mohamed Foysol CHOWDHURY ,  Ilie POENARU

IPC分类号： G01N21/61 ,  G21K5/02 ,  H01L21/02 ,  B82Y15/00

CPC分类号： H05B3/267 ,  G01J3/108 ,  H05B2203/032

摘要： An IR source in the form of a micro-hotplate device including a CMOS metal layer made of at least one layer of embedded on a dielectric membrane supported by a silicon substrate. The device is formed in a CMOS process followed by a back etching step. The IR source also can be in the form of an array of small membranes—closely packed as a result of the use of the deep reactive ion etching technique and having better mechanical stability due to the small size of each membrane while maintaining the same total IR emission level. SOI technology can be used to allow high ambient temperature and allow the integration of a temperature sensor, preferably in the form of a diode or a bipolar transistor right below the IR source.

摘要翻译： 微电子装置形式的IR源，其包括由至少一层嵌入在由硅衬底支撑的电介质膜上的CMOS金属层。 该器件以CMOS工艺形成，随后是背蚀刻步骤。 IR源也可以是由于使用深反应离子蚀刻技术而紧密堆积的小膜阵列的形式，并且由于每个膜的小尺寸而具有更好的机械稳定性，同时保持相同的总IR 排放水平。 可以使用SOI技术来允许高环境温度并且允许温度传感器的集成，优选地在IR源的正下方的二极管或双极晶体管的形式。

公开(公告)号：US20120098082A1

公开(公告)日：2012-04-26

申请号：US13222249

申请日：2011-08-31

申请人： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

发明人： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/66143 ,  H01L21/22 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

摘要翻译： 半导体整流器包括具有第一类导电性的半导体衬底。 形成在基板上的第一层具有第一类导电性，并且比衬底更轻掺杂。 在基板上形成具有第二导电类型的第二层，并且金属层设置在第二层上。 第二层被轻掺杂，使得在金属层和第二层之间形成肖特基接触。 第一电极形成在金属层的上方，第二电极形成在基板的背面。

公开(公告)号：US20080070350A1

公开(公告)日：2008-03-20

申请号：US11873966

申请日：2007-10-17

申请人： Florin UDREA

发明人： Florin UDREA

IPC分类号： H01L21/331

CPC分类号： H01L29/7394 ,  H01L29/0839 ,  H01L29/7432 ,  H01L29/745 ,  H01L29/861 ,  H01L29/872

摘要： A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one. example, a region of the second conductivity type is provided at the second end of the drift region connected directly to the high voltage terminal. In another example, a buffer region of the first conductivity type is provided at the second end of the drift region and a region of a second conductivity type is provided on the other side of the buffer region and connected to the high voltage terminal. Plural electrically floating island regions are provided within the drift region at or towards the second end of the drift region, the plural electrically floating island regions being of the first conductivity type and being more highly doped than the drift region.

摘要翻译： 双极高压/功率半导体器件具有低电压端子和高压端子。 该器件具有第一导电类型的漂移区，并具有第一和第二端。 在一个。 例如，第二导电类型的区域设置在直接连接到高电压端子的漂移区域的第二端。 在另一示例中，第一导电类型的缓冲区设置在漂移区的第二端，并且第二导电类型的区域设置在缓冲区的另一侧并连接到高压端。 在漂移区域内或漂移区域的第二端处设置多个电浮岛区域，多个电浮岛区域是第一导电类型并且比漂移区域更加掺杂。

公开(公告)号：US20110227152A1

公开(公告)日：2011-09-22

申请号：US12909033

申请日：2010-10-21

申请人： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

发明人： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

IPC分类号： H01L27/06

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.

摘要翻译： 功率晶体管的端接结构包括具有有源区和端接区的半导体衬底。 衬底具有第一类导电性。 终端沟槽位于终端区域中并且从有源区域的边界延伸到半导体衬底的边缘的一定距离内。 掺杂区域具有设置在终端沟槽下方的衬底中的第二类型的导电体。 在与边界相邻的侧壁上形成MOS栅极。 掺杂区域从与边界间隔开的部分MOS栅极的下方延伸到终端沟槽的远侧侧壁。 端接结构氧化物层形成在终端沟槽上并且覆盖MOS栅极的一部分并朝向衬底的边缘延伸。 第一导电层形成在半导体衬底的背面上。 第二导电层形成在有源区顶部，MOS栅极的暴露部分的顶部，并延伸以覆盖端接结构氧化物层的至少一部分。

公开(公告)号：US20110227151A1

公开(公告)日：2011-09-22

申请号：US12724771

申请日：2010-03-16

申请人： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

发明人： Chih-Wei HSU ,  Florin UDREA ,  Yih-Yin LIN

IPC分类号： H01L27/06

CPC分类号： H01L29/407 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/404 ,  H01L29/66143 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate and a second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover a portion of the termination structure oxide layer.

摘要翻译： 为功率晶体管提供端接结构。 端接结构包括具有有源区和端接区的半导体衬底。 衬底具有第一类导电性。 终端沟槽位于终端区域中并且从有源区域的边界朝向半导体衬底的边缘延伸。 具有第二类型的导电性的掺杂区域设置在终端沟槽下方的衬底中。 在与边界相邻的侧壁上形成MOS栅极。 掺杂区域从与栅极间隔开的部分MOS栅极向半导体衬底的边缘延伸。 端接结构氧化物层形成在覆盖MOS栅极的一部分并朝向衬底边缘延伸的端接沟槽上。 第一导电层形成在半导体衬底的背侧表面上，并且第二导电层形成在有源区顶部，MOS栅极的暴露部分之上，并延伸以覆盖端接结构氧化物层的一部分。