公开(公告)号：US08423941B2

公开(公告)日：2013-04-16

申请号：US13205186

申请日：2011-08-08

申请人： Fook-Luen Heng ,  Rajiv V. Joshi ,  Alexey Y. Lvov ,  Xiaoping Tang

发明人： Fook-Luen Heng ,  Rajiv V. Joshi ,  Alexey Y. Lvov ,  Xiaoping Tang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.

摘要翻译： 迁移电路布局的方法和系统。 使用表征原始电路的布局结构的约束子集为目标电路构建平面图布局。 通过根据多个不同的缩放比例缩放平面图布局的部分，使得平面图布局的部分与多个不同的缩放比同时缩放，从而在布局图布局上使用基于形状约束的缩放。 细胞被放置在由平面图布局定义的位置处。 使用所有约束来生成迁移的布局，使用基于形状约束的合法化来检查平面图布局。

公开(公告)号：US08276102B2

公开(公告)日：2012-09-25

申请号：US12718567

申请日：2010-03-05

申请人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

发明人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

摘要翻译： 提供了用于估计诸如大规模集成（VLSI）设计的集成电路设计的产量的技术。 一方面，用于确定VLSI查询设计的故障概率的方法包括以下步骤。 构建了一个Voronoi图，它包含一组代表设计的形状。 Voronoi图被转换为包括2t×2s矩形单元格的矩形网格，其中选择t和s，使得一个矩形单元格包含约一个至约五个Voronoi单元。 为网格中的每个单元格计算故障概率。 网格中的单元格成对合并。 重新计算合并的单元的故障概率，这说明了单元之间的空间相关性。 成对合并和重新计算步骤执行s + t次以确定设计失败的概率。

公开(公告)号：US20110219344A1

公开(公告)日：2011-09-08

申请号：US12718567

申请日：2010-03-05

申请人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

发明人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

摘要翻译： 提供了用于估计诸如大规模集成（VLSI）设计的集成电路设计的产量的技术。 一方面，用于确定VLSI查询设计的故障概率的方法包括以下步骤。 构建了一个Voronoi图，它包含一组代表设计的形状。 Voronoi图被转换为包括2t×2s矩形单元格的矩形网格，其中选择t和s，使得一个矩形单元格包含约一个至约五个Voronoi单元。 为网格中的每个单元格计算故障概率。 网格中的单元格成对合并。 重新计算合并的单元的故障概率，这说明了单元之间的空间相关性。 成对合并和重新计算步骤执行s + t次以确定设计失败的概率。

公开(公告)号：US08522173B2

公开(公告)日：2013-08-27

申请号：US13590300

申请日：2012-08-21

申请人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

发明人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows.

摘要翻译： 提供了一种用于估计其上印有多个芯片的晶片的产量的方法，其包括以下步骤。 芯片设计分为多个矩形单元。 为每个单元确定一个处理窗口。 测量晶片上的焦点和剂量值，并用于确定焦点和剂量值的高斯随机分量。 晶片上的焦点和剂量值被表示为焦点和剂量值的系统分量与高斯随机分量之和。 基于芯片的数量估计晶片产量，其中每个点（x，y）的焦点和剂量值被表示为焦点和剂量值的系统分量与高斯随机分量的总和属于 相应的一个进程窗口。

公开(公告)号：US20120311510A1

公开(公告)日：2012-12-06

申请号：US13590300

申请日：2012-08-21

申请人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

发明人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows.

摘要翻译： 提供了一种用于估计其上印有多个芯片的晶片的产量的方法，其包括以下步骤。 芯片设计分为多个矩形单元。 为每个单元确定一个处理窗口。 测量晶片上的焦点和剂量值，并用于确定焦点和剂量值的高斯随机分量。 晶片上的焦点和剂量值被表示为焦点和剂量值的系统分量与高斯随机分量之和。 基于芯片的数量估计晶片产量，其中每个点（x，y）的焦点和剂量值被表示为焦点和剂量值的系统分量与高斯随机分量的总和属于 相应的一个进程窗口。

公开(公告)号：US06986109B2

公开(公告)日：2006-01-10

申请号：US10438625

申请日：2003-05-15

申请人： Robert J. Allen ,  Fook-Luen Heng ,  Alexey Y. Lvov ,  Kevin W. McCullen ,  Sriram Peri ,  Gustavo E. Tellez

发明人： Robert J. Allen ,  Fook-Luen Heng ,  Alexey Y. Lvov ,  Kevin W. McCullen ,  Sriram Peri ,  Gustavo E. Tellez

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.

摘要翻译： 本发明提供了一种修改分层集成电路布局的方法，其中使用这些变量的变量和公式表示分层布局元素的位置，这产生基于公式的分层布局。 这些变量被约束为整数。 本发明提供了一种用于通过与基于公式的分层布局相同的变量定义的目标函数来引导布局的修改的方法。 本发明通过将常数替换为一些变量来简化基于公式的分层布局，使得每个公式被减少到涉及不超过两个剩余变量的表达式。 这产生了简化的布局方程和简化的目标函数。 这也产生了对由常量选择的值组成的分层布局修改的部分解决方案。

公开(公告)号：US08423328B2

公开(公告)日：2013-04-16

申请号：US12570195

申请日：2009-09-30

申请人： John M. Cohn ,  Ulrich A. Finkler ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Fook-Luen Heng ,  Jason D Hibbeler ,  Gie Lee ,  Wayne H. Woods, Jr. ,  Cole E. Zemke

发明人： John M. Cohn ,  Ulrich A. Finkler ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Fook-Luen Heng ,  Jason D Hibbeler ,  Gie Lee ,  Wayne H. Woods, Jr. ,  Cole E. Zemke

IPC分类号： G06F17/17

CPC分类号： G06F17/175

摘要： Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.

摘要翻译： 用空间不均匀的统计学相关性与距离，标准偏差和通过统计学校正的空间插值的平均值来建模随机变量的方法。 该方法包括将统计独立的随机变量分配给坐标系中的一组种子点并在坐标系中的相应空间位置定义多个测试点。 通过从分配给种子点的一个或多个随机变量的空间插值，为每个测试点确定随机变量的等式。 该方法还包括利用相应的校正因子方程来调整每个测试点处的随机变量的方程。

公开(公告)号：US20110077916A1

公开(公告)日：2011-03-31

申请号：US12570195

申请日：2009-09-30

申请人： John M Cohn ,  Ulrich A. Finkler ,  David J. Hathaway ,  Jefrey G. Hemmett ,  Fook-Luen Heng ,  Jason D. Hibbeler ,  Gie Lee ,  Wayne H. Woods, JR. ,  Cole E. Zemke

发明人： John M Cohn ,  Ulrich A. Finkler ,  David J. Hathaway ,  Jefrey G. Hemmett ,  Fook-Luen Heng ,  Jason D. Hibbeler ,  Gie Lee ,  Wayne H. Woods, JR. ,  Cole E. Zemke

IPC分类号： G06F17/10 ,  G06F17/17 ,  G06F1/02

CPC分类号： G06F17/175

摘要： Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.

摘要翻译： 用空间不均匀的统计学相关性与距离，标准偏差和通过统计学校正的空间插值的平均值来建模随机变量的方法。 该方法包括将统计独立的随机变量分配给坐标系中的一组种子点并在坐标系中的相应空间位置定义多个测试点。 通过从分配给种子点的一个或多个随机变量的空间插值，为每个测试点确定随机变量的等式。 该方法还包括利用相应的校正因子方程来调整每个测试点处的随机变量的方程。

公开(公告)号：US07882463B2

公开(公告)日：2011-02-01

申请号：US12035572

申请日：2008-02-22

申请人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

发明人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.

摘要翻译： 本发明包括通过以下方式选择性地缩放集成电路（IC）设计的解决方案：层，区域或单元，或它们的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了使设计人员提高产量的需要。

公开(公告)号：US20080148210A1

公开(公告)日：2008-06-19

申请号：US12035572

申请日：2008-02-22

申请人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

发明人： Fook-Luen Heng ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Rani R. Narayan ,  Stephen L. Runyon ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.

摘要翻译： 本发明包括通过以下方式选择性地缩放集成电路（IC）设计的解决方案：层，区域或单元，或它们的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了使设计人员提高产量的需要。