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公开(公告)号：US07761675B2
公开(公告)日：2010-07-20
申请号：US11432301
申请日：2006-05-10
申请人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
发明人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
IPC分类号： G06F12/00
CPC分类号： G11C16/22 , G06F12/1433 , G06F21/6209 , G06F21/79 , G06F2212/2022
摘要： A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.
摘要翻译： 闪存类型的非易失性存储器件包括用于存储数据的第一存储器单元，用于存储第一存储器单元的保护信息的第二存储器单元，以及用于更新保护信息的电路，其包括用于写入多个版本的电路 第二存储器单元中的保护信息，以及用于识别当前版本的保护信息的电路。
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公开(公告)号：US20070016735A1
公开(公告)日：2007-01-18
申请号：US11432301
申请日：2006-05-10
申请人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
发明人： Francesco Mastroianni , Antonino Mondello , Elena Cussotto , Massimiliano Mollichelli , Mauro Sali
CPC分类号： G11C16/22 , G06F12/1433 , G06F21/6209 , G06F21/79 , G06F2212/2022
摘要： A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.
摘要翻译： 闪存类型的非易失性存储器件包括用于存储数据的第一存储器单元，用于存储第一存储器单元的保护信息的第二存储器单元，以及用于更新保护信息的电路，其包括用于写入多个版本的电路 第二存储器单元中的保护信息，以及用于识别当前版本的保护信息的电路。
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公开(公告)号：US20120137049A1
公开(公告)日：2012-05-31
申请号：US12956660
申请日：2010-11-30
CPC分类号： G06F12/0246 , G06F8/66
摘要： Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored n a trap address register.
摘要翻译： 本文描述的示例性实施例可以包括至少部分地响应于代码获取地址和存储在陷阱地址寄存器中的地址之间的匹配而将非易失性存储器设备内的固件执行转移到一个或多个替换指令。
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公开(公告)号：US07515493B2
公开(公告)日：2009-04-07
申请号：US11739167
申请日：2007-04-24
IPC分类号： G11C7/02
摘要： A sensing circuit is provided. The sensing circuit is adapted to determine when a cell current flowing trough a selected memory cell exceeds a reference current during an evaluation phase of a sensing operation. The sensing circuit is adapted to be coupled to at least one selected memory cell through a respective bit line. The sensing circuit includes: an access circuit node adapted to be coupled to the bit line; precharging circuitry adapted to be activated in a precharge phase of the sensing operation preceding the evaluation phase, so as to bring a voltage of said access circuit node to a reference voltage; a reference circuit node coupled to the access circuit node and arranged to receive the reference current. The sensing circuit further includes an evaluation circuit node coupled to the reference circuit node through a first current to voltage converter, adapted to sink a current flowing from the reference circuit node to the evaluation circuit node and to produce a corresponding voltage difference between the reference circuit node and the evaluation circuit node, wherein the current is nearly equal to the reference current substantially at the end of the precharge phase; comparator circuitry is provided, adapted to compare the voltage of the access circuit node with the voltage of the evaluation circuit node and to provide a corresponding comparison signal whose time pattern indicates when the cell current exceeds the reference current. The first current to voltage converter is an electronic device having essentially the behavior of a diode.
摘要翻译： 提供感测电路。 感测电路适于确定在感测操作的评估阶段期间流过所选择的存储器单元的单元电流何时超过参考电流。 感测电路适于通过相应的位线耦合到至少一个选择的存储器单元。 感测电路包括：适于耦合到位线的接入电路节点; 预充电电路，其适于在所述评估阶段之前的所述感测操作的预充电阶段中被激活，以使所述访问电路节点的电压达到参考电压; 参考电路节点，其耦合到所述接入电路节点并被布置成接收所述参考电流。 感测电路还包括通过第一电流 - 电压转换器耦合到参考电路节点的评估电路节点，适于吸收从参考电路节点流向评估电路节点的电流，并产生参考电路之间的相应电压差 节点和评估电路节点，其中电流几乎等于基本上在预充电阶段结束时的参考电流; 提供比较器电路，用于将访问电路节点的电压与评估电路节点的电压进行比较，并提供对应的比较信号，其时间模式指示电池电流何时超过参考电流。 第一个电流到电压转换器是具有基本上二极管行为的电子器件。
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公开(公告)号：US07400281B2
公开(公告)日：2008-07-15
申请号：US11681659
申请日：2007-03-02
申请人： Roberto Versari , Massimiliano Mollichelli , Nicola Del Gatto , Nicola Rosito , Emanuele Confalonieri
发明人： Roberto Versari , Massimiliano Mollichelli , Nicola Del Gatto , Nicola Rosito , Emanuele Confalonieri
IPC分类号： H03M1/10
CPC分类号： H03M1/0607 , H03M1/785
摘要： A regulator for a digital-to-analog converter having in input a digital signal and suitable for providing an analog signal in output, the regulator including at least one pair of buffers having in input the digital signal and the outputs connected to a pair of circuit branches connected to the output of the regulator; each of the at least two circuit branches having at least one resistance. To at least one of the at least one pair of buffers a variable resistance is associated, and the regulator includes a circuit having in input the analog signal and adapted for measuring its waveform and acting on the variable resistance in response to its possible anomalous waveform compared to a desired waveform.
摘要翻译： 一种用于数模转换器的调节器，其具有输入数字信号并且适于在输出中提供模拟信号，所述调节器包括至少一对缓冲器，所述至少一对缓冲器具有输入中的数字信号和连接到一对电路的输出 分支连接到调节器的输出端; 所述至少两个电路分支中的每一个具有至少一个电阻。 对于至少一对缓冲器中的至少一个，可变电阻相关联，并且调节器包括具有输入模拟信号并适于测量其波形的电路并且响应于其可能的异常波形而作用于可变电阻 到期望的波形。
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6.发明授权Memory device and method of operating the same with high rejection of the noise on the high-voltage supply line 有权存储器件和操作方法与高压电源线上的高噪声抑制相同公开(公告)号：US07324379B2
公开(公告)日：2008-01-29
申请号：US11241729
申请日：2005-09-30
摘要： A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.
摘要翻译： 存储器件具有存储器单元阵列。 列解码器被配置为寻址存储器单元。 电荷泵供应电路为列解码器产生升压的电源电压。 连接级布置在电源电路和列解码器之间。 连接级在高阻抗状态和低阻抗状态之间切换，并且被配置为在存储器件的给定操作条件下，特别是在读取步骤期间切换到高阻抗状态。
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公开(公告)号：US07388793B2
公开(公告)日：2008-06-17
申请号：US11280803
申请日：2005-11-16
IPC分类号： G11C7/10
CPC分类号： G11C16/30
摘要： A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.
摘要翻译： 通过识别单元的至少第一和第二操作区域并将第一和第二操作区域与存储器单元的相应的第一和第二操作条件相关联来配置连接到存储器单元的电压调节器。 检测涉及编程操作的存储单元的操作状态，并且产生至少根据所述检测到的操作条件的调节器的配置信号，该配置信号采取与第一和第二操作相关联的第一和第二值 条件。
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公开(公告)号：US20070285999A1
公开(公告)日：2007-12-13
申请号：US11739167
申请日：2007-04-24
IPC分类号： G11C5/14
摘要： A sensing circuit is provided. The sensing circuit is adapted to determine when a cell current flowing trough a selected memory cell exceeds a reference current during an evaluation phase of a sensing operation. The sensing circuit is adapted to be coupled to at least one selected memory cell through a respective bit line. The sensing circuit includes: an access circuit node adapted to be coupled to the bit line; precharging circuitry adapted to be activated in a precharge phase of the sensing operation preceding the evaluation phase, so as to bring a voltage of said access circuit node to a reference voltage; a reference circuit node coupled to the access circuit node and arranged to receive the reference current. The sensing circuit further includes an evaluation circuit node coupled to the reference circuit node through a first current to voltage converter, adapted to sink a current flowing from the reference circuit node to the evaluation circuit node and to produce a corresponding voltage difference between the reference circuit node and the evaluation circuit node, wherein the current is nearly equal to the reference current substantially at the end of the precharge phase; comparator circuitry is provided, adapted to compare the voltage of the access circuit node with the voltage of the evaluation circuit node and to provide a corresponding comparison signal whose time pattern indicates when the cell current exceeds the reference current. The first current to voltage converter is an electronic device having essentially the behavior of a diode.
摘要翻译： 提供感测电路。 感测电路适于确定在感测操作的评估阶段期间流过所选择的存储器单元的单元电流何时超过参考电流。 感测电路适于通过相应的位线耦合到至少一个选择的存储器单元。 感测电路包括：适于耦合到位线的接入电路节点; 预充电电路，其适于在所述评估阶段之前的所述感测操作的预充电阶段中被激活，以使所述访问电路节点的电压达到参考电压; 参考电路节点，其耦合到所述接入电路节点并被布置成接收所述参考电流。 感测电路还包括通过第一电流 - 电压转换器耦合到参考电路节点的评估电路节点，适于吸收从参考电路节点流向评估电路节点的电流，并产生参考电路之间的相应电压差 节点和评估电路节点，其中电流几乎等于基本上在预充电阶段结束时的参考电流; 提供比较器电路，用于将访问电路节点的电压与评估电路节点的电压进行比较，并提供对应的比较信号，其时间模式指示电池电流何时超过参考电流。 第一个电流到电压转换器是具有基本上二极管行为的电子器件。
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9.发明申请Memory device and method for operating the same with high rejection of the noise on the high-voltage supply line 有权用于高压电源线上高噪声抑制的操作的存储器件和方法公开(公告)号：US20060171204A1
公开(公告)日：2006-08-03
申请号：US11241729
申请日：2005-09-30
IPC分类号： G11C16/04
摘要： A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.
摘要翻译： 存储器件具有存储器单元阵列。 列解码器被配置为寻址存储器单元。 电荷泵供应电路为列解码器产生升压的电源电压。 连接级布置在电源电路和列解码器之间。 连接级在高阻抗状态和低阻抗状态之间切换，并且被配置为在存储器件的给定操作条件下，特别是在读取步骤期间切换到高阻抗状态。
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公开(公告)号：US08607210B2
公开(公告)日：2013-12-10
申请号：US12956660
申请日：2010-11-30
IPC分类号： G06F9/45
CPC分类号： G06F12/0246 , G06F8/66
摘要： Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.
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