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1.发明授权Direct control of operation blocks using operand signal of control instruction as extension to instruction set in a hardwired control processor 有权使用控制指令的操作数信号直接控制操作块，作为硬连线控制处理器中指令集的扩展公开(公告)号：US06505294B2
公开(公告)日：2003-01-07
申请号：US09998568
申请日：2001-11-16
IPC分类号： G06F930
CPC分类号： G06F9/30181 , G06F9/30003 , G06F9/30145
摘要： A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the normal path in which normal instructions are interpreted. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.
摘要翻译： 处理器设置有一组通常由操作部分和操作数部分形成的指令。 对于特殊控制指令，操作数部分沿着与正常指令解释的正常路径分开的旁路路径被发送到操作块。 以这种方式，可以实现该组指令的扩展，以便根据用户自己的要求定制指令集。 因此，处理器控制单元应该能够在接收到一个这样的指令时将其输出耦合到其输入，从而在没有解释的情况下传送这样的内部操作控制信号。
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2.发明授权Processor with a control instruction for sending control signals without interpretation for extension of instruction set 有权具有用于发送控制信号的控制指令的处理器，无需解释用于指令集的扩展公开(公告)号：US06389528B2
公开(公告)日：2002-05-14
申请号：US09221300
申请日：1998-12-23
IPC分类号： G06F930
CPC分类号： G06F9/30181 , G06F9/30003 , G06F9/30145
摘要： A processor is provided with a set of instructions formed in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the normal path in which normal instructions are interpreted. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.
摘要翻译： 处理器设置有一组通常由操作部分和操作数部分形成的指令。 对于特殊控制指令，操作数部分沿着与正常指令解释的正常路径分开的旁路路径被发送到操作块。 以这种方式，可以实现该组指令的扩展，以便根据用户自己的要求定制指令集。 因此，处理器控制单元应该能够在接收到一个这样的指令时将其输出耦合到其输入，从而在没有解释的情况下传送这样的内部操作控制信号。
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公开(公告)号：US08174419B2
公开(公告)日：2012-05-08
申请号：US12719424
申请日：2010-03-08
IPC分类号： H03M1/00
CPC分类号： G06F13/28
摘要： An analog-digital converter for converting an analog signal into a digital signal includes a first configuration register for configuring a first group of channels and a second configuration register for configuring a second group of channels. The conversion result of the channels of the first group is transferred to a memory via a direct memory access. Each channel of the second group of channels has an associated respective data register and the conversion results of the channels of the second group are stored in the respective data registers.
摘要翻译： 一种用于将模拟信号转换为数字信号的模拟数字转换器包括用于配置第一组信道的第一配置寄存器和用于配置第二组信道的第二配置寄存器。 第一组的通道的转换结果通过直接存储器访问传送到存储器。 第二组信道的每个信道具有关联的相应的数据寄存器，并且第二组的信道的转换结果存储在相应的数据寄存器中。
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公开(公告)号：US20100245148A1
公开(公告)日：2010-09-30
申请号：US12719424
申请日：2010-03-08
IPC分类号： H03M1/12
CPC分类号： G06F13/28
摘要： An analog-digital converter for converting an analog signal into a digital signal includes a first configuration register for configuring a first group of channels and a second configuration register for configuring a second group of channels. The conversion result of the channels of the first group is transferred to a memory via a direct memory access. Each channel of the second group of channels has an associated respective data register and the conversion results of the channels of the second group are stored in the respective data registers.
摘要翻译： 一种用于将模拟信号转换为数字信号的模拟数字转换器包括用于配置第一组信道的第一配置寄存器和用于配置第二组信道的第二配置寄存器。 第一组的通道的转换结果通过直接存储器访问传送到存储器。 第二组信道的每个信道具有关联的相应的数据寄存器，并且第二组的信道的转换结果存储在相应的数据寄存器中。
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5.发明授权Communication system for a control channel, and corresponding method and computer program product 有权控制通道的通信系统，以及相应的方法和计算机程序产品公开(公告)号：US08762590B2
公开(公告)日：2014-06-24
申请号：US12830162
申请日：2010-07-02
申请人： Ugo Mari , Francesco Bombaci , Pietro Cusmano , Sonia Sfasciotti
发明人： Ugo Mari , Francesco Bombaci , Pietro Cusmano , Sonia Sfasciotti
IPC分类号： G06F3/00
CPC分类号： G09G5/006 , G06F1/3237 , G09G2370/12 , Y02D10/128 , Y02D50/20
摘要： A communication system for an HDMI communication interface CEC channel includes a communication module for receiving messages via the CEC channel, a processing unit for processing the received messages and an oscillator for driving the communication module. When the interface is in an active mode, the system is operative to activate the timer upon detection of the start of transmission of a first message, detect the initial bit of the first message, reconstruct and process the first message, and switch the interface from the active mode to standby by deactivating the oscillator. When the interface is in standby, the system is operative to switch the interface to the active condition by activating the oscillator and the timer when the start of a transmission of a second message is detected, detect the initial bit of a transmission of the second message, and reconstruct and process the second message.
摘要翻译： 用于HDMI通信接口CEC通道的通信系统包括用于经由CEC信道接收消息的通信模块，用于处理接收的消息的处理单元和用于驱动通信模块的振荡器。 当接口处于活动模式时，系统可操作以在检测到第一消息的发送开始时检测定时器，检测第一消息的初始位，重新构建和处理第一消息，并将接口从 通过停用振荡器来激活待机模式。 当接口处于待机状态时，系统通过在检测到第二个消息的发送开始时激活振荡器和定时器来将接口切换到活动状态，检测第二消息的传输的初始位 ，并重建和处理第二个消息。
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6.发明授权Method and system for configuring registers in microcontrollers, and corresponding computer-program product 有权用于在微控制器中配置寄存器的方法和系统，以及相应的计算机程序产品公开(公告)号：US07571379B2
公开(公告)日：2009-08-04
申请号：US11301372
申请日：2005-12-12
CPC分类号： G06F11/167
摘要： A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the datum in the first register and the logic complement in the second register, and, where the identity is not verified, generates a signal indicating that the data have been corrupted by a disturbance. The system also includes a final-state machine which disables the comparator during writing of the registers.
摘要翻译： 用于配置微控制器寄存器的系统包括第一寄存器和第二寄存器。 该系统包括用于将数据加载到第一寄存器中的数据源和第二寄存器中的所述数据的逻辑补码。 该系统还包括一个比较器，用于验证第一个寄存器中的数据和第二个寄存器中的逻辑补码之间的标识，并且在该身份未被验证的情况下，生成一个信号，指示数据已被干扰破坏。 该系统还包括在寄存器写入期间禁止比较器的最终状态机。
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7.发明申请CIRCUIT FOR PROGRAMMING SAMPLING TIME IN A MULTICHANNEL ANALOG-TO-DIGITAL CONVERTER 审中-公开用于在多通道模拟数字转换器中编程采样时间的电路公开(公告)号：US20080224907A1
公开(公告)日：2008-09-18
申请号：US12035606
申请日：2008-02-22
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03M1/1225
摘要： The sampling time in a multichannel analog-to-digital converter is programmed with a circuit comprising a memory register with memory locations, which can be respectively coupled to the channels of the converter. The memory locations of the register are able to store a signal identifying a sampling-time value selected for each individual channel of the converter. The circuit likewise comprises a converter module coupled to the memory register for converting the signal identifying the sampling-time value into a corresponding signal for driving the respective channel of the converter for a sampling time corresponding to the sampling time selected. The circuit can be actuated in a synchronized way with the converter so as to vary selectively the sampling time applied to the channels of the converter in the course of operation.
摘要翻译： 多通道模数转换器中的采样时间由包括存储器位置的存储器寄存器的电路编程，存储器位置可以分别耦合到转换器的通道。 寄存器的存储器位置能够存储识别为转换器的每个独立通道选择的采样时间值的信号。 电路同样包括耦合到存储器寄存器的转换器模块，用于将标识采样时间值的信号转换成对应的信号，用于驱动转换器的相应通道，以对应于所选择的采样时间。 该电路可以与转换器同步地启动，以便在操作过程中选择性地改变施加到转换器通道的采样时间。
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公开(公告)号：US20060236173A1
公开(公告)日：2006-10-19
申请号：US11301372
申请日：2005-12-12
IPC分类号： G01R31/28
CPC分类号： G06F11/167
摘要： A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the datum in the first register and the logic complement in the second register, and, where the identity is not verified, generates a signal indicating that the data have been corrupted by a disturbance. The system also includes a final-state machine which disables the comparator during writing of the registers.
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9.发明授权Digital interface for driving at least a couple of power elements, in particular in PWM applications 有权用于驱动至少一对功率元件的数字接口，特别是在PWM应用中公开(公告)号：US07034479B2
公开(公告)日：2006-04-25
申请号：US10746118
申请日：2003-12-24
IPC分类号： H02P7/29
CPC分类号： H02M7/53873
摘要： A digital interface for driving at least one complementary pair of first and second power elements connected in an inverter configuration between first and second voltage references is provided. The digital interface includes a first input terminal for receiving a PWM input signal, a first counter stage connected to the first input terminal, and a second counter stage connected to an output of the first counter stage. A toggle stage is connected to the first input terminal and to an output of the second counter stage. A first output terminal is connected to an output of the toggle stage, and is to be connected to a control terminal of the first power element. A second output terminal is connected to the output of the first counter stage for receiving a delayed PWM output signal therefrom, and is to be connected to a control terminal of the second power element. The toggle stage generates a second PWM output signal for the first output terminal. The second PWM output signal is kept at a desired low level in correspondence with switching of the PWM input signal having a lower duration than a predetermined duration.
摘要翻译： 提供了用于驱动在第一和第二电压基准之间以逆变器配置连接的至少一对互补互补对的第一和第二功率元件的数字接口。 数字接口包括用于接收PWM输入信号的第一输入端，连接到第一输入端的第一计数级，以及连接到第一计数级的输出的第二计数级。 触发级连接到第一输入端子和第二计数器级的输出端。 第一输出端子连接到肘节级的输出，并且连接到第一功率元件的控制端子。 第二输出端子连接到第一计数器级的输出端，用于从其接收延迟的PWM输出信号，并且连接到第二功率元件的控制端子。 触发级产生用于第一输出端的第二PWM输出信号。 对应于具有比预定持续时间更短的持续时间的PWM输入信号的切换，第二PWM输出信号保持在期望的低电平。
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10.发明申请COMMUNICATION SYSTEM FOR A CONTROL CHANNEL, AND CORRESPONDING METHOD AND COMPUTER PROGRAM PRODUCT 有权用于控制信道的通信系统，以及相应的方法和计算机程序产品公开(公告)号：US20110026613A1
公开(公告)日：2011-02-03
申请号：US12830162
申请日：2010-07-02
申请人： Ugo MARI , Francesco Bombaci , Pietro Cusmano , Sonia Sfasciotti
发明人： Ugo MARI , Francesco Bombaci , Pietro Cusmano , Sonia Sfasciotti
IPC分类号： H04L27/00
CPC分类号： G09G5/006 , G06F1/3237 , G09G2370/12 , Y02D10/128 , Y02D50/20
摘要： A communication system for an HDMI communication interface CEC channel includes a communication module for receiving messages via the CEC channel, a processing unit for processing the received messages and an oscillator for driving the communication module. When the interface is in an active mode, the system is operative to activate the timer upon detection of the start of transmission of a first message, detect the initial bit of the first message, reconstruct and process the first message, and switch the interface from the active mode to standby by deactivating the oscillator. When the interface is in standby, the system is operative to switch the interface to the active condition by activating the oscillator and the timer when the start of a transmission of a second message is detected, detect the initial bit of a transmission of the second message, and reconstruct and process the second message.
摘要翻译： 用于HDMI通信接口CEC通道的通信系统包括用于经由CEC信道接收消息的通信模块，用于处理接收的消息的处理单元和用于驱动通信模块的振荡器。 当接口处于活动模式时，系统可操作以在检测到第一消息的发送开始时检测定时器，检测第一消息的初始位，重新构建和处理第一消息，并将接口从 通过停用振荡器来激活待机模式。 当接口处于待机状态时，系统通过在检测到第二个消息的发送开始时激活振荡器和定时器来将接口切换到活动状态，检测第二消息的传输的初始位 ，并重建和处理第二个消息。
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