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公开(公告)号：US20060139109A1
公开(公告)日：2006-06-29
申请号：US11235787
申请日：2005-09-27
Applicant: Alain Oustaloup , Yann Deval , Didier Belot , Pierre Melchior , Jean-Baptiste Begueret , Franck Badets , Vincent Lagareste
Inventor： Alain Oustaloup , Yann Deval , Didier Belot , Pierre Melchior , Jean-Baptiste Begueret , Franck Badets , Vincent Lagareste
IPC: H03L7/00
CPC classification number: H03L7/093 , H03H7/06 , H03L7/0891 , H03L7/18
Abstract: The frequency synthesizer includes a phase-locked loop (PLL). The PLL includes an oscillator controlled to deliver an output signal at a predefined output frequency, a variable frequency divider to convert the output signal into a divided-frequency signal, a phase comparator to produce a signal measuring a phase difference between the divided-frequency signal and a reference signal at a reference frequency, and a loop filter to control the oscillator on the basis of the measurement signal. To increase the speed of convergence of the synthesizer if the set point is changed, the loop filter of the PLL is a fractional, i.e. non-integer, order low-pass filter.
Abstract translation: 频率合成器包括锁相环（PLL）。 PLL包括被控制以以预定的输出频率传送输出信号的振荡器，用于将输出信号转换成分频信号的可变分频器，相位比较器，以产生测量分频信号之间的相位差的信号 以及参考频率的参考信号，以及环路滤波器，用于根据测量信号控制振荡器。 为了增加合成器的收敛速度，如果设定点改变，PLL的环路滤波器是分数即非整数阶低通滤波器。
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2.发明申请公开(公告)号：US20080205486A1
公开(公告)日：2008-08-28
申请号：US12012499
申请日：2008-01-31
Applicant: Franck Badets , David Marchaland
Inventor： Franck Badets , David Marchaland
CPC classification number: H04B1/7176 , H04B1/7174
Abstract: An embodiment of the invention relates to a method for transmission by ultra-wide-band pulses of digital data formed with a flow of information elements, this method comprising at least one operation including sequentially encoding the information elements by modulating an oscillating signal In order to avoid the use of a bandpass filter, the oscillating signal is modulated in amplitude depending on the identity or dissimilarity of each information element relative to the preceding information element.
Abstract translation: 本发明的实施例涉及一种用信息元素流形成的数字数据的超宽带脉冲进行传输的方法，该方法包括至少一种操作，包括通过调制振荡信号对信息元素进行顺序编码，以便 避免使用带通滤波器，根据每个信息元素相对于先前信息元素的标识或不相似性，振幅信号的幅度被调制。
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公开(公告)号：US08867696B2
公开(公告)日：2014-10-21
申请号：US13172491
申请日：2011-06-29
Applicant: Nicolas Regimbal , Franck Badets , Yann Deval , Jean-Baptiste Begueret
Inventor： Nicolas Regimbal , Franck Badets , Yann Deval , Jean-Baptiste Begueret
CPC classification number: H03K5/156 , H03K21/10 , H03K23/662 , H03K23/68
Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.
Abstract translation: 一种分数分频器，包括用于产生具有针对原始定时信号的每k个脉冲具有j个脉冲的降频定时信号的分频单元，其中j和k各自是整数; 以及相位校正电路，其适于选择性地将所述降频定时信号的第j个脉冲移位第一固定时间段。
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公开(公告)号：US20090066428A1
公开(公告)日：2009-03-12
申请号：US12171159
申请日：2008-07-10
Applicant: Franck Badets
Inventor： Franck Badets
CPC classification number: H03B19/00 , B82Y25/00 , H01F10/325 , H01F10/329 , H03B2201/025
Abstract: A circuit for providing an A.C. signal including a number N of nanomagnetic oscillators, N being an integer greater than or equal to 2, each nanomagnetic oscillator providing a periodic signal; a unit for providing a control signal that can take N values, each periodic signal being associated with one of the values of the control signal; and a multiplexer receiving the N periodic signals and the control signal and providing the A.C. signal equal to one of the periodic signals according to the value of the control signal.
Abstract translation: 一种用于提供包括N个纳米磁性振荡器的交流信号的电路，N是大于或等于2的整数，每个纳米磁性振荡器提供周期性信号; 用于提供可以取N个值的控制信号的单元，每个周期信号与控制信号的值之一相关联; 以及多路复用器，其接收所述N个周期信号和所述控制信号，并且根据所述控制信号的值提供等于所述周期信号之一的所述交流信号。
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公开(公告)号：US08884709B2
公开(公告)日：2014-11-11
申请号：US13547594
申请日：2012-07-12
Applicant: Franck Badets , Serge Ramet , Michel Ayraud
Inventor： Franck Badets , Serge Ramet , Michel Ayraud
CPC classification number: H03C3/0908
Abstract: A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode.
Abstract translation: 锁相环双点调制器可以包括具有可以通过第一调制信号改变的比率的分频器和可以通过与第一调制信号相关的第二调制信号来改变其频率的振荡器。 校准电路可以在校准模式下被配置为基于用于第二调制信号的两个不同校准值的振荡器的频率测量来匹配第一和第二调制信号的增益。 锁相双点调制器还可以包括具有大于1的恒定比率并置于第二调制信号的路径中的衰减器，以及配置为由校准电路控制的选择器开关，以减小衰减器 在校准模式下。
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Patent Agency Ranking
公开(公告)号：US20120001665A1
公开(公告)日：2012-01-05
申请号：US13172491
申请日：2011-06-29
Applicant: Nicolas Regimbal , Franck Badets , Yann Deval , Jean-Baptiste Begueret
Inventor： Nicolas Regimbal , Franck Badets , Yann Deval , Jean-Baptiste Begueret
IPC: H03K21/00
CPC classification number: H03K5/156 , H03K21/10 , H03K23/662 , H03K23/68
Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.
Abstract translation: 一种分数分频器，包括用于产生具有针对原始定时信号的每k个脉冲具有j个脉冲的降频定时信号的分频单元，其中j和k各自是整数; 以及相位校正电路，其适于选择性地将所述降频定时信号的第j个脉冲移位第一固定时间段。
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公开(公告)号：US07315214B2
公开(公告)日：2008-01-01
申请号：US11400062
申请日：2006-04-07
Applicant: Franck Badets , Didier Belot , Vincent Lagareste , Yann Deval , Pierre Melchior , Jean-Baptiste Begueret
Inventor： Franck Badets , Didier Belot , Vincent Lagareste , Yann Deval , Pierre Melchior , Jean-Baptiste Begueret
CPC classification number: H03L7/093 , H03L7/087 , H03L7/0893 , H03L7/18 , H03L2207/06
Abstract: A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.
Abstract translation: 锁相环包括用于以确定的输出频率输出输出信号的受控振荡器和用于将输出信号转换为分频的信号的可变分频器。 PLL被称为复合，因为它包括至少一个具有环路滤波器的第一环路，该环路滤波器基于分频频率的信号产生用于振荡器的第一控制信号，以及具有不同于环路的环路滤波器的第二环路 滤波器，用于基于分频后的信号产生用于对振荡器进行附加控制的第二信号。 第一回路的环路滤波器和第二回路的环路滤波器具有不同的各自的截止频率。 第一个环路的通带可以适应于确保PLL的收敛和稳定性，而第二个环路可以提供额外的通带，在修改输出预置值的情况下可以提高PLL的自适应速度 频率。
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8.发明授权公开(公告)号：US08374280B2
公开(公告)日：2013-02-12
申请号：US12012499
申请日：2008-01-31
Applicant: Franck Badets , David Marchaland
Inventor： Franck Badets , David Marchaland
IPC: H04L27/00
CPC classification number: H04B1/7176 , H04B1/7174
Abstract: An embodiment of the invention relates to a method for transmission by ultra-wide-band pulses of digital data formed with a flow of information elements, this method comprising at least one operation including sequentially encoding the information elements by modulating an oscillating signal In order to avoid the use of a bandpass filter, the oscillating signal is modulated in amplitude depending on the identity or dissimilarity of each information element relative to the preceding information element.
Abstract translation: 本发明的实施例涉及一种用信息元素流形成的数字数据的超宽带脉冲进行传输的方法，该方法包括至少一种操作，包括通过调制振荡信号对信息元素进行顺序编码，以便 避免使用带通滤波器，根据每个信息元素相对于先前信息元素的标识或不相似性，振幅信号的幅度被调制。
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公开(公告)号：US20130015892A1
公开(公告)日：2013-01-17
申请号：US13547594
申请日：2012-07-12
Applicant: Franck Badets , Serge Ramet , Michel Ayraud
Inventor： Franck Badets , Serge Ramet , Michel Ayraud
CPC classification number: H03C3/0908
Abstract: A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode.
Abstract translation: 锁相环双点调制器可以包括具有可以通过第一调制信号改变的比率的分频器和可以通过与第一调制信号相关的第二调制信号来改变其频率的振荡器。 校准电路可以在校准模式下被配置为基于用于第二调制信号的两个不同校准值的振荡器的频率测量来匹配第一和第二调制信号的增益。 锁相双点调制器还可以包括具有大于1的恒定比率并置于第二调制信号的路径中的衰减器，以及配置为由校准电路控制的选择器开关，以减小衰减器 在校准模式下。
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公开(公告)号：US20090128198A1
公开(公告)日：2009-05-21
申请号：US12254617
申请日：2008-10-20
Applicant: Franck Badets , Thomas Finateu
Inventor： Franck Badets , Thomas Finateu
IPC: H03B21/00
Abstract: A digital frequency synthesizer receiving a first signal corresponding to a periodic sequence of first pulses at a first frequency and providing a second signal corresponding to a periodic sequence of second pulses at a second frequency. The synthesizer includes a first circuit clocked by a third signal corresponding to a sequence of third pulses and obtained from the first signal, the first circuit providing a fourth digital signal which, for any set of third successive pulses, increases (decreases) on each pulse and decreases (increases) at the end of said set; and a second circuit receiving the first and fourth signals and providing, for each first pulse from among some at least of the first pulses, a second pulse which is shifted with respect to the first pulse by a duration which depends on the fourth signal.
Abstract translation: 数字频率合成器，以第一频率接收对应于第一脉冲的周期性序列的第一信号，并提供对应于第二频率的第二脉冲的周期性序列的第二信号。 合成器包括由第三信号对应的第三信号的第一电路，该信号对应于从第一信号获得的第三脉冲序列，第一电路提供第四数字信号，对于任何一组第三连续脉冲，在每个脉冲上增加（减小） 并在所述集合的末尾减小（增加）; 以及第二电路，接收所述第一和第四信号，并且对于所述第一脉冲中的至少一些中的每个第一脉冲提供相对于所述第一脉冲移位了取决于所述第四信号的持续时间的第二脉冲。
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