利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

17 条记录 (耗时 0.02 秒)

    PLL-based frequency synthesizer
    1.
    发明申请
    PLL-based frequency synthesizer 审中-公开
    基于PLL的频率合成器

    公开(公告)号：US20060139109A1

    公开(公告)日：2006-06-29

    申请号：US11235787

    申请日：2005-09-27

    申请人： Alain Oustaloup ,  Yann Deval ,  Didier Belot ,  Pierre Melchior ,  Jean-Baptiste Begueret ,  Franck Badets ,  Vincent Lagareste

    发明人： Alain Oustaloup ,  Yann Deval ,  Didier Belot ,  Pierre Melchior ,  Jean-Baptiste Begueret ,  Franck Badets ,  Vincent Lagareste

    IPC分类号： H03L7/00

    CPC分类号： H03L7/093 ,  H03H7/06 ,  H03L7/0891 ,  H03L7/18

    摘要： The frequency synthesizer includes a phase-locked loop (PLL). The PLL includes an oscillator controlled to deliver an output signal at a predefined output frequency, a variable frequency divider to convert the output signal into a divided-frequency signal, a phase comparator to produce a signal measuring a phase difference between the divided-frequency signal and a reference signal at a reference frequency, and a loop filter to control the oscillator on the basis of the measurement signal. To increase the speed of convergence of the synthesizer if the set point is changed, the loop filter of the PLL is a fractional, i.e. non-integer, order low-pass filter.

    摘要翻译： 频率合成器包括锁相环（PLL）。 PLL包括被控制以以预定的输出频率传送输出信号的振荡器，用于将输出信号转换成分频信号的可变分频器，相位比较器，以产生测量分频信号之间的相位差的信号 以及参考频率的参考信号，以及环路滤波器，用于根据测量信号控制振荡器。 为了增加合成器的收敛速度，如果设定点改变，PLL的环路滤波器是分数即非整数阶低通滤波器。

    Phase locked loop
    2.
    发明申请
    Phase locked loop 有权
    锁相环

    公开(公告)号：US20060232344A1

    公开(公告)日：2006-10-19

    申请号：US11400062

    申请日：2006-04-07

    申请人： Franck Badets ,  Didier Belot ,  Vincent Lagareste ,  Yann Deval ,  Pierre Melchior ,  Jean-Baptiste Begueret

    发明人： Franck Badets ,  Didier Belot ,  Vincent Lagareste ,  Yann Deval ,  Pierre Melchior ,  Jean-Baptiste Begueret

    IPC分类号： H03L7/00

    CPC分类号： H03L7/093 ,  H03L7/087 ,  H03L7/0893 ,  H03L7/18 ,  H03L2207/06

    摘要： A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

    摘要翻译： 锁相环包括用于以确定的输出频率输出输出信号的受控振荡器和用于将输出信号转换为分频的信号的可变分频器。 PLL被称为复合，因为它包括至少一个具有环路滤波器的第一环路，该环路滤波器基于分频频率的信号产生用于振荡器的第一控制信号，以及具有不同于环路的环路滤波器的第二环路 滤波器，用于基于分频后的信号产生用于对振荡器进行附加控制的第二信号。 第一回路的环路滤波器和第二回路的环路滤波器具有不同的各自的截止频率。 第一个环路的通带可以适应于确保PLL的收敛和稳定性，而第二个环路可以提供额外的通带，在修改输出预置值的情况下可以提高PLL的自适应速度 频率。

    Phase locked loop
    3.
    发明授权
    Phase locked loop 有权
    锁相环

    公开(公告)号：US07315214B2

    公开(公告)日：2008-01-01

    申请号：US11400062

    申请日：2006-04-07

    申请人： Franck Badets ,  Didier Belot ,  Vincent Lagareste ,  Yann Deval ,  Pierre Melchior ,  Jean-Baptiste Begueret

    发明人： Franck Badets ,  Didier Belot ,  Vincent Lagareste ,  Yann Deval ,  Pierre Melchior ,  Jean-Baptiste Begueret

    IPC分类号： H03L7/00 ,  H03L7/07 ,  H03L7/087

    CPC分类号： H03L7/093 ,  H03L7/087 ,  H03L7/0893 ,  H03L7/18 ,  H03L2207/06

    摘要： A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

    摘要翻译： 锁相环包括用于以确定的输出频率输出输出信号的受控振荡器和用于将输出信号转换为分频的信号的可变分频器。 PLL被称为复合，因为它包括至少一个具有环路滤波器的第一环路，该环路滤波器基于分频频率的信号产生用于振荡器的第一控制信号，以及具有不同于环路的环路滤波器的第二环路 滤波器，用于基于分频后的信号产生用于对振荡器进行附加控制的第二信号。 第一回路的环路滤波器和第二回路的环路滤波器具有不同的各自的截止频率。 第一个环路的通带可以适应于确保PLL的收敛和稳定性，而第二个环路可以提供额外的通带，在修改输出预置值的情况下可以提高PLL的自适应速度 频率。

    FRACTIONAL FREQUENCY DIVIDER
    5.
    发明申请
    FRACTIONAL FREQUENCY DIVIDER 有权
    分数分频器

    公开(公告)号：US20120001665A1

    公开(公告)日：2012-01-05

    申请号：US13172491

    申请日：2011-06-29

    申请人： Nicolas Regimbal ,  Franck Badets ,  Yann Deval ,  Jean-Baptiste Begueret

    发明人： Nicolas Regimbal ,  Franck Badets ,  Yann Deval ,  Jean-Baptiste Begueret

    IPC分类号： H03K21/00

    CPC分类号： H03K5/156 ,  H03K21/10 ,  H03K23/662 ,  H03K23/68

    摘要： A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

    摘要翻译： 一种分数分频器，包括用于产生具有针对原始定时信号的每k个脉冲具有j个脉冲的降频定时信号的分频单元，其中j和k各自是整数; 以及相位校正电路，其适于选择性地将所述降频定时信号的第j个脉冲移位第一固定时间段。

    Device and Method for Generating a Signal of Parametrizable Frequency
    7.
    发明申请
    Device and Method for Generating a Signal of Parametrizable Frequency 有权
    用于产生可参数频率信号的装置和方法

    公开(公告)号：US20120062288A1

    公开(公告)日：2012-03-15

    申请号：US13229478

    申请日：2011-09-09

    申请人： Didier Belot ,  Pierre-Olivier Lucas De Peslouan ,  Cédric Majek ,  Yann Deval ,  Thierry Taris ,  Jean-Baptiste Begueret

    发明人： Didier Belot ,  Pierre-Olivier Lucas De Peslouan ,  Cédric Majek ,  Yann Deval ,  Thierry Taris ,  Jean-Baptiste Begueret

    IPC分类号： H03L7/08

    CPC分类号： H03L7/0812 ,  H03L7/0995 ,  H03L7/1974

    摘要： Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider.

    摘要翻译： 用于生成包括参考信号的发生器的锁相环的参数化频率信号的装置，包括用于接收参考信号的第一输入的相位 - 频率比较器，基于由相位信号输出的结果输出的振荡器， 频率比较器，耦合在振荡器的输出和相位 - 频率比较器的第二输入端之间的分数分频器，以及选择器，选择性地将振荡器的输入与发生器的输入或振荡器的输出相连， 分数分频器的倍率的函数。

    Device and method for generating a signal of parametrizable frequency
    8.
    发明授权
    Device and method for generating a signal of parametrizable frequency 有权
    用于产生可参数频率信号的装置和方法

    公开(公告)号：US08502574B2

    公开(公告)日：2013-08-06

    申请号：US13229478

    申请日：2011-09-09

    申请人： Didier Belot ,  Pierre-Olivier Lucas De Peslouan ,  Cédric Majek ,  Yann Deval ,  Thierry Taris ,  Jean-Baptiste Begueret

    发明人： Didier Belot ,  Pierre-Olivier Lucas De Peslouan ,  Cédric Majek ,  Yann Deval ,  Thierry Taris ,  Jean-Baptiste Begueret

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/0995 ,  H03L7/1974

    摘要： Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider.

    摘要翻译： 用于生成包括参考信号的发生器的锁相环的参数化频率信号的装置，包括用于接收参考信号的第一输入的相位 - 频率比较器，基于由相位信号输出的结果输出的振荡器， 频率比较器，耦合在振荡器的输出和相位 - 频率比较器的第二输入端之间的分数分频器，以及选择器，选择性地将振荡器的输入与发生器的输入或振荡器的输出相连， 分数分频器的倍率的函数。