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    SWITCHING ARRANGEMENT AND METHOD WITH SEPARATED OUTPUT BUFFERS
    4.
    发明申请
    SWITCHING ARRANGEMENT AND METHOD WITH SEPARATED OUTPUT BUFFERS 有权
    具有分离输出缓冲器的切换布局和方法

    公开(公告)号：US20110149729A1

    公开(公告)日：2011-06-23

    申请号：US12947887

    申请日：2010-11-17

    申请人： Alan Benner ,  Antonius Engberson ,  Gottfried Goldrian ,  Ronald Luijten

    发明人： Alan Benner ,  Antonius Engberson ,  Gottfried Goldrian ,  Ronald Luijten

    IPC分类号： H04L12/56 ,  H04L12/26

    CPC分类号： H04L49/3081 ,  H04L49/203 ,  H04L2012/5635 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04Q11/0478

    摘要： A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.

    摘要翻译： 交换设备能够根据数据分组目的地信息将到达的数据分组路由到专用输出端口。 对于开关装置中的每组输入端口，开关装置具有一组具有输出缓冲器的输出缓冲器，用于在输出缓冲器中的与相同组的输出缓冲器相关联的地址处存储每个数据分组的有效载荷;以及 属于专用输出端口。 输出缓冲器中的至少一个具有一组输出队列，其具有用于每个输出端口的输出队列，用于存储存储在相应输出缓冲器中的每个有效载荷的地址。 仲裁器控制存储的地址的读出顺序。 对于与同一组输出端口相关的输出缓冲器，复用器根据读出顺序将输出缓冲器的有效载荷复用到输出端口。

    Switching arrangement and method with separated output buffers
    5.
    发明授权
    Switching arrangement and method with separated output buffers 有权
    具有分离输出缓冲器的开关布置和方法

    公开(公告)号：US08644327B2

    公开(公告)日：2014-02-04

    申请号：US12947887

    申请日：2010-11-17

    申请人： Alan Benner ,  Antonius Engberson ,  Gottfried Goldrian ,  Ronald Luijten

    发明人： Alan Benner ,  Antonius Engberson ,  Gottfried Goldrian ,  Ronald Luijten

    IPC分类号： H04L12/28 ,  H04L12/56

    CPC分类号： H04L49/3081 ,  H04L49/203 ,  H04L2012/5635 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04Q11/0478

    摘要： A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.

    摘要翻译： 交换设备能够根据数据分组目的地信息将到达的数据分组路由到专用输出端口。 对于开关装置中的每组输入端口，开关装置具有一组具有输出缓冲器的输出缓冲器，用于在输出缓冲器中的与相同组的输出缓冲器相关联的地址处存储每个数据分组的有效载荷;以及 属于专用输出端口。 输出缓冲器中的至少一个具有一组输出队列，其具有用于每个输出端口的输出队列，用于存储存储在相应输出缓冲器中的每个有效载荷的地址。 仲裁器控制存储的地址的读出顺序。 对于与同一组输出端口相关的输出缓冲器，复用器根据读出顺序将输出缓冲器的有效载荷复用到输出端口。

    Method and apparatus for testing and evaluation of distributed networks
    6.
    发明授权
    Method and apparatus for testing and evaluation of distributed networks 失效
    分布式网络的测试和评估方法和装置

    公开(公告)号：US5271000A

    公开(公告)日：1993-12-14

    申请号：US804133

    申请日：1991-12-06

    申请人： Antonius J. Engbersen ,  Marco Heddes ,  Andreas Herkersdorf ,  Ronald Luijten ,  Ernst Rothauser

    发明人： Antonius J. Engbersen ,  Marco Heddes ,  Andreas Herkersdorf ,  Ronald Luijten ,  Ernst Rothauser

    IPC分类号： H04L12/26 ,  H04L12/56 ,  H04Q11/04 ,  H04L1/24

    CPC分类号： H04L43/50 ,  H04L12/2697 ,  H04Q11/0478 ,  H04L2012/5628

    摘要： The dynamic functional behavior of geographically distributed fast packet switching systems, including those which accommodate high-priority circuit switched traffic and low-priority packet switched traffic, are tested in real-time by sending test packets from one or more source nodes through the system to specific destinations that comprise a test packet analyzer. The test packets have the same structure as the data packets, but in their payload portion carry the entire information required to perform the testing. The nature of that test information depends on the characteristics of a set of predefined system errors the verification system is supposed to identify. For detecting errors, the test information would include an input address indicating the source of the test packet, a sequence number defining the order in which the packet should arrive at the destination, time bits relating to the packet length and/or to the expected packet transmission delay, and a cyclic redundancy code which covers the entire contents of the test packet, including its control portion. Each analyzer at a receiving station operates autonomously from the senders and processes all received traffic in real-time; this enables it to recognize all defined system errors, even those occurring with very low probability, at the packet level.

    High speed buffer management of share memory using linked lists and plural buffer managers for processing multiple requests concurrently
    8.
    发明授权
    High speed buffer management of share memory using linked lists and plural buffer managers for processing multiple requests concurrently 失效
    使用链表对共享存储器进行高速缓冲管理，并且多个缓冲管理器同时处理多个请求

    公开(公告)号：US5432908A

    公开(公告)日：1995-07-11

    申请号：US313656

    申请日：1994-09-27

    申请人： Marco Heddes ,  Ronald Luijten

    发明人： Marco Heddes ,  Ronald Luijten

    IPC分类号： G06F12/02 ,  G06F5/06 ,  G06F12/08 ,  G06F13/12 ,  G06F13/14

    CPC分类号： G06F5/06 ,  G06F2205/064

    摘要： The present invention relates to the management of a large and fast memory. The memory is logically subdivided into several smaller parts called buffers. A buffer-control memory (11) having as many sections for buffer-control records as buffers exist is employed together with a buffer manager (12). The buffer manager (12) organizes and controls the buffers by keeping the corresponding buffer-control records in linked lists. A request manager (20), as pad of the buffer manager (12), does or does not grant the allocation of a buffer. A stack manager (21) controls the free buffers by keeping the buffer-control records in a stack (23.1), and a FIFO manager (22) keeps the buffer-control records of allocated buffers in FIFO linked lists (23.2-23.n). The stack and FIFO managers (20), (21) are parts of the buffer manager (12), too.

    摘要翻译： 本发明涉及大型和快速存储器的管理。 存储器在逻辑上细分为几个称为缓冲器的较小部件。 缓冲器管理器（12）与缓冲器控制存储器（11）一起使用，缓冲器控制存储器（11）具有与存储缓冲器控制记录一样多的部分。 缓冲管理器（12）通过将相应的缓冲器控制记录保持在链表中来组织和控制缓冲器。 作为缓冲器管理器（12）的焊盘的请求管理器（20）执行或不准许缓冲器的分配。 堆栈管理器（21）通过将缓冲器控制记录保持在堆栈（23.1）中来控制空闲缓冲器，并且FIFO管理器（22）将分配的缓冲器的缓冲器控制记录保持在FIFO链接列表中（23.2-23.n ）。 栈和FIFO管理器（20），（21）也是缓冲管理器（12）的一部分。

    Transmitter-receiver crossbar for a packet switch
    9.
    发明申请
    Transmitter-receiver crossbar for a packet switch 审中-公开
    分组交换机的发射机 - 接收机交叉开关

    公开(公告)号：US20070286190A1

    公开(公告)日：2007-12-13

    申请号：US11803803

    申请日：2007-05-16

    申请人： Wolfgang Denzel ,  Ronald Luijten ,  Thomas Morf ,  Martin Schmatz

    发明人： Wolfgang Denzel ,  Ronald Luijten ,  Thomas Morf ,  Martin Schmatz

    IPC分类号： H04L12/56

    CPC分类号： H04L49/101

    摘要： A transmitter-receiver crossbar for a packet switch comprising a transmitter having an array of transmitting ports, each having one or more transmitting antennas to transmit a radio signal and a receiver having an array of receiving ports, each having one or more receiving antennas to receive the radio signal.

    摘要翻译： 一种用于分组交换机的发射机 - 接收机交叉开关，包括具有发射端口阵列的发射机，每个发射端口具有一个或多个发射天线以发射无线电信号，以及具有接收端阵列的接收机，每个接收端口具有一个或多个接收天线以接收 无线电信号。

    Configurable gigabits switch adapter
    10.
    发明授权
    Configurable gigabits switch adapter 失效
    可配置千兆开关适配器

    公开(公告)号：US5311509A

    公开(公告)日：1994-05-10

    申请号：US832127

    申请日：1992-02-06

    申请人： Marco Heddes ,  Ronald Luijten

    发明人： Marco Heddes ,  Ronald Luijten

    IPC分类号： H04L29/06 ,  H04L12/56

    CPC分类号： H04L49/3081 ,  H04L49/20 ,  H04L49/3063 ,  H04L2012/5653 ,  H04L49/30 ,  H04L49/55

    摘要： The present invention relates to a data transmission system and concerns a method for transforming user frames into fixed length cells, e.g. ATM (Asynchronous Transfer Mode), such that the fixed length cells can be transported through a cell handling switch fabric (11). A hardware implementation of this method consists of two parts, a transmitter (12.1) and a receiver (13.1), both being part of a switching subsystem (10) comprising a switch fabric (11). The transmitter (12.1) buffers user data and segments them into fixed length cells to be transported through said switch (11). The receiver part (13.1) reassembles user data on reception of these cells.

    摘要翻译： 本发明涉及一种数据传输系统，涉及将用户帧转换为固定长度小区的方法，例如， ATM（异步传输模式），使得固定长度的小区可以通过小区处理交换结构（11）传输。 该方法的硬件实现包括两个部分：发射机（12.1）和接收机（13.1），它们都是包括交换结构（11）的交换子系统（10）的一部分。 发射机（12.1）缓冲用户数据并将它们分段成固定长度的小区，以便通过所述交换机（11）传输。 接收器部分（13.1）在接收到这些单元时重新组合用户数据。