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1.发明授权Secure computing device including virtual memory table look-aside buffer with non-relocatable page of memory 有权安全计算设备包括具有不可重定位页面的内存的虚拟内存表查看缓冲区公开(公告)号：US06567906B2
公开(公告)日：2003-05-20
申请号：US09827851
申请日：2001-04-06
IPC分类号： G06F1200
CPC分类号： G06F21/64 , G06F12/145 , G06F21/51 , G06F21/575 , G06F2207/7219 , G06F2211/008 , G06F2211/1097
摘要： A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.
摘要翻译： 诊断程序可以检查程序的安全性。 程序存储在存储器中预定的不可重定位的物理地址。 加载诊断程序并按照标准检查预定物理地址的程序。 然后，诊断程序指示如果程序符合标准或未验证为安全（如果不符合标准），则该程序被证实为安全的。 如果程序未被证实为安全的，则诊断程序可以采取补救措施，例如禁用程序的正常操作，通过系统调制解调器发送预定的消息，或通过调制解调器下载程序的另一个副本。 使用具有固定虚拟地址寄存器和对应的固定物理地址寄存器的特殊表格后备缓冲器使该程序不可重定位。
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2.发明授权Secure computing device including operating system stored in non-relocatable page of memory 有权安全计算设备，包括存储在不可重定位的存储器页面中的操作系统公开(公告)号：US06266754B1
公开(公告)日：2001-07-24
申请号：US09314397
申请日：1999-05-19
IPC分类号： G06F1210
CPC分类号： G06F21/64 , G06F12/145 , G06F21/51 , G06F21/575 , G06F2207/7219 , G06F2211/008 , G06F2211/1097
摘要： A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.
摘要翻译： 诊断程序可以检查程序的安全性。 程序存储在存储器中预定的不可重定位的物理地址。 加载诊断程序并按照标准检查预定物理地址的程序。 然后，诊断程序指示如果程序符合标准或未验证为安全（如果不符合标准），则该程序被证实为安全的。 如果程序没有被证实为安全的，则诊断程序可以采取补救措施，例如禁用程序的正常操作，通过系统调制解调器发送预定的消息，或通过调制解调器下载程序的另一副本。 使用具有固定虚拟地址寄存器和对应的固定物理地址寄存器的特殊表格后备缓冲器使该程序不可重定位。
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公开(公告)号：US06310657B1
公开(公告)日：2001-10-30
申请号：US09679000
申请日：2000-10-04
申请人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号： H04N550
CPC分类号： H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要： An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.
摘要翻译： 其中CPU在工作存储器空间中生成窗口的屏幕显示系统还提供对工作存储器空间中的窗口地址的实时计算。 这可以消除对单独的帧缓冲存储器的需要。
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公开(公告)号：US5835793A
公开(公告)日：1998-11-10
申请号：US851168
申请日：1997-05-02
CPC分类号： G06F9/30018 , G06F12/04
摘要： A data processing device uses a portion of a random access memory as an input buffer 114 for holding a portion of a stream of data which is being processed by a processing unit within the processing device. A Get Bit-Field instruction is provided which directs the processing unit to extract selected bit fields from the data stream stored in the input buffer. A register R6 holds a bit address which points to the end of a selected bit field, while a register R0 holds the width of the selected bit field. An address register is connected to a register R6 in a manner that allows data words to be accessed in input buffer 114 using only a word portion of the bit address. A funnel shifter 203 is disposed to extract the selected bit field from concatenated data words in response to a bit address portion of the bit address in register R6.
摘要翻译： 数据处理装置使用随机存取存储器的一部分作为输入缓冲器114，用于保持由处理装置内的处理单元处理的数据流的一部分。 提供获取位字段指令，其指示处理单元从存储在输入缓冲器中的数据流中提取所选位字段。 寄存器R6保持指向所选位字段结束的位地址，而寄存器R0保持所选位字段的宽度。 地址寄存器以只允许位地址的字部分在输入缓冲器114中访问数据字的方式连接到寄存器R6。 漏斗移位器203设置成响应于寄存器R6中的位地址的位地址部分从连接的数据字中提取所选择的位域。
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5.发明授权
公开(公告)号：US5657423A
公开(公告)日：1997-08-12
申请号：US54768
申请日：1993-04-26
申请人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
发明人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
摘要： A data processing system (10) uses a microprocessor host (12) coupled to a decoding system (14). A hardware filter arithmetic unit block (32) retrieves decoded information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). An address circuit forms several addresses from a single value to accesses multiple sources of data and coefficients simultaneously for use by the hardware filter arithmetic unit.
摘要翻译： 数据处理系统（10）使用耦合到解码系统（14）的微处理器主机（12）。 硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索解码信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 地址电路从单个值形成多个地址以同时访问数据和系数的多个源，以供硬件滤波器运算单元使用。
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6.发明授权Secure computing device having boot read only memory verification of program code 有权安全计算设备具有启动只读程序代码的内存验证公开(公告)号：US06775778B1
公开(公告)日：2004-08-10
申请号：US09314398
申请日：1999-05-19
IPC分类号： G06F1136
CPC分类号： G06F21/51 , G06F21/575 , G06F21/64
摘要： A secure computing system stores a program, preferably the real time operating system, that is encrypted with a private key. A boot ROM on the same integrated circuit as the data processor and inaccessible from outside includes an initialization program and a public key corresponding to the private key. On initialization the boot ROM decrypts at least a verification portion of the program. This enables verification or non-verification of the security of the program. The boot ROM may store additional public keys for verification of application programs following verification of the real time operating system. Alternatively, these additional public keys may be stored in the nonvolatile memory. On verification of the security of the program, normal operation is enabled. On non-verification, system could be disabled, or that application program could be disabled. The system could notify the system vendor of the security violation using the modem of the secure computing system. This technique is applicable to downloaded programs could be applied to after sale acquired application programs. On downloading the after acquired program they decrypted using an additional public key.
摘要翻译： 安全计算系统存储用私钥加密的程序，优选实时操作系统。 在与数据处理器相同的集成电路上并且不能从外部访问的引导ROM包括初始化程序和与私钥对应的公开密钥。 在初始化时，引导ROM至少解密程序的验证部分。 这使得能够验证或不验证程序的安全性。 启动ROM可以存储用于验证实时操作系统的应用程序的附加公钥。 或者，这些额外的公钥可以存储在非易失性存储器中。 在验证程序的安全性时，启用正常操作。 在不验证时，可以禁用系统，或者该应用程序可以被禁用。 该系统可以使用安全计算系统的调制解调器向系统供应商通知安全违规。 这种技术适用于下载的程序可以应用于售后收购应用程序。 在下载后获得的程序时，他们使用附加的公钥进行解密。
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公开(公告)号：US5963596A
公开(公告)日：1999-10-05
申请号：US857976
申请日：1997-05-16
摘要： A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译： 公开了一种数据处理系统（10），其包括耦合到解码系统（14）的微处理器主机（12）。 主机接口块（18）接收比特流并将比特流传送到系统解码器块（20）。 系统解码器块（20）从比特流中提取适当的数据，并加载输入缓冲器（24）或可选的外部缓冲器（26）。 音频解码器块（28）从输入缓冲器（24）检索数据，并生成比例因子索引，存储在运算单元缓冲器（30）中的每码字值比特和子带样本。 硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 PCM缓冲器（34）内的数据由PCM输出块（36）输出到数 - 模转换器（16）。
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公开(公告)号：US5794181A
公开(公告)日：1998-08-11
申请号：US824072
申请日：1997-03-24
申请人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
发明人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
摘要： A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译： 公开了一种数据处理系统（10），其包括耦合到解码系统（14）的微处理器主机（12）。 主机接口块（18）接收比特流并将比特流传送到系统解码器块（20）。 系统解码器块（20）从比特流中提取适当的数据，并加载输入缓冲器（24）或可选的外部缓冲器（26）。 音频解码器块（28）从输入缓冲器（24）检索数据，并生成比例因子索引，存储在运算单元缓冲器（30）中的每码字值比特和子带样本。 硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 PCM缓冲器（34）内的数据由PCM输出块（36）输出到数 - 模转换器（16）。
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公开(公告)号：US5568495A
公开(公告)日：1996-10-22
申请号：US484418
申请日：1995-06-07
CPC分类号： G06F17/10
摘要： An audio data processing system (10) is described which comprises a control processor (12) coupled to an execution controller (22) through a bus (21). The control processor (12) serves as a master processor to control the operation of the execution controller (22) which in turn controls the operation of a multiplier accumulator (28). An ancillary data handler (20) is provided to retrieve ancillary data from an input FIFO buffer (18). Audio data is retrieved from the input FIFO buffer (18) by the control processor (12) and processed audio data is output through an output block (30).
摘要翻译： 描述了音频数据处理系统（10），其包括通过总线（21）耦合到执行控制器（22）的控制处理器（12）。 控制处理器（12）用作主处理器，以控制执行控制器（22）的操作，继而控制乘法器累加器（28）的操作。 提供辅助数据处理器（20）以从输入FIFO缓冲器（18）检索辅助数据。 通过控制处理器（12）从输入FIFO缓冲器（18）检索音频数据，并通过输出块（30）输出处理后的音频数据。
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10.发明授权公开(公告)号：US06961715B1
公开(公告)日：2005-11-01
申请号：US09652895
申请日：2000-08-31
CPC分类号： G06T1/60
摘要： A data processing device uses a portion of a random access memory as an input buffer for holding a portion of a stream of data which is being processed by a processing unit within the processing device. Various break-point source tasks 801a–n determine discontinuities in the portion of data stored in the input buffer and a sorted list of the addresses of the discontinuities is maintained in breakpoint queue 800. Since the buffer is managed in a FIFO manner, a single breakpoint register 810 is sufficient to monitor addresses as they are provided by an address register 820 for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task 802.
摘要翻译： 数据处理装置使用随机存取存储器的一部分作为输入缓冲器，用于保持由处理装置内的处理单元处理的数据流的一部分。 各种断点源任务801a-n确定存储在输入缓冲器中的数据部分中的不连续性，并且在断点队列800中保持不连续性地址的排序列表。 由于以FIFO方式管理缓冲器，所以单个断点寄存器810足以监视地址寄存器820提供的用于访问随机存取存储器的地址。 当检测到断点时，更新任务802更新断点队列和断点寄存器。
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