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1.发明授权Systems and methods for reducing the effect of noise while reading data from memory 有权用于在从存储器读取数据的同时降低噪声的影响的系统和方法公开(公告)号：US06678197B1
公开(公告)日：2004-01-13
申请号：US10273623
申请日：2002-10-18
申请人： Frederick A. Perner , Kenneth K. Smith , David H. McIntyre , Sarah M. Brandenberger , Terrel R. Munden , Robert Sesek
发明人： Frederick A. Perner , Kenneth K. Smith , David H. McIntyre , Sarah M. Brandenberger , Terrel R. Munden , Robert Sesek
IPC分类号： G11C702
CPC分类号： G11C7/02 , G11C7/06 , G11C7/1006
摘要： Systems and methods for reducing the effect of noise while reading data from memory, are provided. One system embodiment includes a memory cell that stores a first data; multiple sensing devices that receive the first data and provide a first set of outputs; and a voting system that evaluates the first set of outputs to determine whether one of the outputs of the first set is valid data from the memory cell. One method embodiment includes reading data in parallel that is stored in a memory cell to provide outputs; and evaluating the outputs to determine whether one of the outputs is valid data from the memory cell.
摘要翻译： 提供了用于在从存储器读取数据的同时降低噪声的影响的系统和方法。 一个系统实施例包括存储第一数据的存储单元; 多个感测装置，其接收第一数据并提供第一组输出; 以及投票系统，其评估所述第一组输出以确定所述第一组的输出中的一个是来自所述存储器单元的有效数据。 一种方法实施例包括并行读取存储在存储单元中以提供输出的数据; 以及评估所述输出以确定所述输出中的一个是来自所述存储器单元的有效数据。
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公开(公告)号：US06625055B1
公开(公告)日：2003-09-23
申请号：US10120113
申请日：2002-04-09
申请人： Kenneth K. Smith , Sarah M. Brandenberger , Darrel R. Bloomquist , Kenneth J. Eldredge , Andrew L. Van Brocklin , Peter J. Fricke
发明人： Kenneth K. Smith , Sarah M. Brandenberger , Darrel R. Bloomquist , Kenneth J. Eldredge , Andrew L. Van Brocklin , Peter J. Fricke
IPC分类号： G11C1100
CPC分类号： G11C11/5692
摘要： A read-only memory device is described having non-volatile memory cells that include a memory component connected between electrically conductive traces. A memory component is formed to include a resistor that indicates a resistance value when a potential is applied to a selected memory cell. The resistance value of a memory component in an individual memory cell corresponds to multiple logical bits. The resistance value of a memory component corresponding to a set of logical bits can be based on a thickness and/or an area of electrically resistive material that forms the memory component, and/or based on the geometric shape of the memory component, where different geometric shapes of the electrically resistive material have different resistance values that correspond to different sets of logical bits.
摘要翻译： 描述了只读存储器件，其具有包括连接在导电迹线之间的存储器部件的非易失性存储器单元。 存储器部件形成为包括当电位被施加到所选择的存储器单元时指示电阻值的电阻器。 单个存储单元中的存储器组件的电阻值对应于多个逻辑位。 对应于一组逻辑位的存储器组件的电阻值可以基于形成存储器组件的电阻材料的厚度和/或面积，和/或基于存储器组件的几何形状，其中不同 电阻材料的几何形状具有不同的电阻值，其对应于不同的逻辑位组。
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公开(公告)号：US06570782B1
公开(公告)日：2003-05-27
申请号：US10050668
申请日：2002-01-16
IPC分类号： G11C1700
CPC分类号： G11C17/00
摘要： Methods for storing a bit sequence are provided. A representative method for storing a bit sequence includes converting a first bit sequence containing a first number of low-resistance bits into a second bit sequence containing a second number of low-resistance bits that is lower than the first number of low-resistance bits, and then storing the second bit sequence in a resistance-based memory device. Systems, computer-readable media, and other methods for storing and retrieving a bit sequence are also provided.
摘要翻译： 提供了存储位序列的方法。 用于存储位序列的代表性方法包括将包含第一数量的低电阻位的第一位序列转换为包含低于第一数量的低电阻位的第二数量的低电阻位的第二位序列， 然后将第二比特序列存储在基于电阻的存储装置中。 还提供了用于存储和检索比特序列的系统，计算机可读介质和其他方法。
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公开(公告)号：US07027318B2
公开(公告)日：2006-04-11
申请号：US10449572
申请日：2003-05-30
IPC分类号： G11C11/00
CPC分类号： G11C5/147
摘要： A method and apparatus are disclosed for adjusting the offset voltage of a circuit. In one embodiment, the method comprises: supplying reference and supply voltages to the circuit, controlling a voltage across a memory element to be approximately equal to the reference voltage, comparing the current through the memory element to a predetermined value, and adjusting an offset voltage of the circuit, where the offset may remain substantially constant despite changes in the supply voltage.
摘要翻译： 公开了一种用于调整电路的偏移电压的方法和装置。 在一个实施例中，该方法包括：向电路提供参考电压和电源电压，将存储元件两端的电压控制为近似等于参考电压，将通过存储元件的电流与预定值进行比较，并调整偏移电压 的电路，其中尽管电源电压发生变化，但是偏移可能保持基本恒定。
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5.发明授权System for and method of accessing a four-conductor magnetic random access memory 有权访问四导体磁性随机存取存储器的系统和方法公开(公告)号：US06839270B2
公开(公告)日：2005-01-04
申请号：US10346494
申请日：2003-01-17
CPC分类号： G11C11/16
摘要： A control circuit for writing to and reading from MRAMs comprising a row decoder; a first read/write row driver connected to the row decoder; a plurality of global row write conductors connected to the first read/write row driver; a plurality of row taps connected to each of the global row write conductors; and a second read/write row driver connected to the global row write conductors.
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公开(公告)号：US06751147B1
公开(公告)日：2004-06-15
申请号：US10635399
申请日：2003-08-05
IPC分类号： G11C1115
CPC分类号： G11C11/15
摘要： A method of adaptively writing magnetic memory cells of a MRAM is disclosed according to an embodiment of the present invention. The method comprises providing a logical data block of a memory array having magnetic memory cells, each magnetic memory cell in a known initial state and each magnetic memory cell configured along an easy-axis magnetic field generating conductor and writing to the magnetic memory cells using a predefined minimum current level. The method may further comprise sensing the magnetic memory cells to determine if data has been successfully written, incrementing the current level if writing was unsuccessful and repeating above.
摘要翻译： 根据本发明的实施例公开了一种自适应地写入MRAM的磁存储单元的方法。 该方法包括提供具有磁存储单元的存储器阵列的逻辑数据块，具有已知初始状态的每个磁存储单元和沿着易轴磁场产生导体配置的每个磁存储单元，并使用 预定义的最小电流电平。 该方法还可以包括感测磁存储器单元以确定数据是否已被成功写入，如果写入不成功并在上面重复，则递增当前电平。
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公开(公告)号：US06958933B2
公开(公告)日：2005-10-25
申请号：US10784514
申请日：2004-02-23
CPC分类号： G11C11/15
摘要： A data storage device comprising a first memory cell string that includes at least a first magnetic random access memory (MRAM) cell coupled to a second MRAM cell and a circuit coupled to a node between the first MRAM cell and the second MRAM cell is provided. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and in response to a write sense current being applied across the first MRAM cell.
摘要翻译： 一种包括第一存储器单元串的数据存储设备，其包括至少耦合到第二MRAM单元的第一磁随机存取存储器（MRAM）单元和耦合到第一MRAM单元和第二MRAM单元之间的节点的电路。 电路被配置为响应于提供给存储器单元串的电压以及响应于跨第一MRAM单元施加的写入感测电流来检测节点处的电压变化。
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公开(公告)号：US06947313B2
公开(公告)日：2005-09-20
申请号：US10649076
申请日：2003-08-27
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/15
摘要： Method and apparatus for coupling conductors in magnetic memory. In some embodiments, the memory element comprises: a first magnetic memory element, a first group of conductors magnetically coupled to the first magnetic memory element, a second magnetic memory element, a second group of conductors magnetically coupled to the second magnetic memory element, where the second magnetic memory element is substantially vertical to the first, and the first and second group of conductors have at least one conductor in common.
摘要翻译： 在磁存储器中耦合导体的方法和装置。 在一些实施例中，存储元件包括：第一磁存储元件，磁耦合到第一磁存储元件的第一组导体，第二磁存储元件，与第二磁存储器元件磁耦合的第二组导体， 第二磁存储元件基本上垂直于第一磁存储元件，并且第一和第二组导体具有至少一个共同的导体。
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公开(公告)号：US06901005B2
公开(公告)日：2005-05-31
申请号：US10649752
申请日：2003-08-27
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/22
CPC分类号： G11C11/15
摘要： Methods and apparatuses are disclosed for reducing the read time of a memory array. In one embodiment, the method includes sampling unknown data values from a plurality of memory elements, buffering the unknown values, writing known values to the plurality of memory elements and sampling the known values, and comparing the known values to the buffered values.
摘要翻译： 公开了用于减少存储器阵列的读取时间的方法和装置。 在一个实施例中，该方法包括从多个存储器元件采样未知数据值，缓冲未知值，将已知值写入多个存储器元件并对已知值进行采样，以及将已知值与缓冲值进行比较。
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公开(公告)号：US07913130B2
公开(公告)日：2011-03-22
申请号：US10698896
申请日：2003-10-31
CPC分类号： G11C29/02 , G11C29/026
摘要： A data storage device includes non-volatile memory; and a read circuit for performing multi-sample read operations on the memory during a normal mode of operation. The read circuit includes a digital counter having an output that indicates a single bit (e.g., a sign-bit). The read circuit allows an external device (e.g., a memory tester) to supply test clock pulses to an input of the digital counter during a test mode. The test clock pulses can be counted to determine a state of the digital counter.
摘要翻译： 数据存储装置包括非易失性存储器; 以及用于在正常操作模式期间对存储器执行多样本读取操作的读取电路。 读取电路包括具有指示单个位（例如，符号位）的输出的数字计数器。 读取电路允许外部设备（例如，存储器测试器）在测试模式期间将测试时钟脉冲提供给数字计数器的输入。 可以对测试时钟脉冲进行计数，以确定数字计数器的状态。
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