公开(公告)号：US08195907B2

公开(公告)日：2012-06-05

申请号：US12258680

申请日：2008-10-27

申请人： Frederick A. Ware ,  Ian Shaeffer ,  Scott C. Best ,  Craig E. Hampel

发明人： Frederick A. Ware ,  Ian Shaeffer ,  Scott C. Best ,  Craig E. Hampel

IPC分类号： G06F1/08 ,  G06F13/16

CPC分类号： G06F13/4243

摘要： This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance.

摘要翻译： 本公开提供了一种用于在可重构存储器系统中调整系统定时的方法。 在动态点对点（“DPP”）系统中，例如，制造商提供的系统定时参数，例如访问延迟和最大时钟速度通常反映最坏情况的配置方案。 通过原位检测实际配置（例如，是否插入了扩展板），并且相应地将系统配置为以特定配置的方式运行，可能排除最坏情况或接近最坏情况的情况，系统时序 可以重新定义参数以达到比常规级别更高的性能; DPP系统尤其如此，其中信号路径通常随着附加模块的添加而变得更直接。 因此，与惯例智慧相反，这可能决定组件扩展应该减慢时序，如果配置支持，这样的系统实际上可以增加时钟速度，以获得更好的性能。

公开(公告)号：US20090164677A1

公开(公告)日：2009-06-25

申请号：US12258680

申请日：2008-10-27

申请人： Frederick A. Ware ,  Ian Shaeffer ,  Scott C. Best ,  Craig E. Hampel

发明人： Frederick A. Ware ,  Ian Shaeffer ,  Scott C. Best ,  Craig E. Hampel

IPC分类号： G06F1/04 ,  G06F13/00

CPC分类号： G06F13/4243

摘要： This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance.

摘要翻译： 本公开提供了一种用于在可重构存储器系统中调整系统定时的方法。 在动态点对点（“DPP”）系统中，例如，制造商提供的系统定时参数，例如访问延迟和最大时钟速度通常反映最坏情况的配置方案。 通过原位检测实际配置（例如，是否插入了扩展板），并且相应地将系统配置为以特定配置的方式运行，可能排除最坏情况或接近最坏情况的情况，系统时序 可以重新定义参数以达到比常规级别更高的性能; DPP系统尤其如此，其中信号路径通常随着附加模块的添加而变得更直接。 因此，与惯例智慧相反，这可能决定组件扩展应该减慢时序，如果配置支持，这样的系统实际上可以增加时钟速度，以获得更好的性能。

公开(公告)号：US20110016278A1

公开(公告)日：2011-01-20

申请号：US12920811

申请日：2009-03-05

申请人： Frederick Ware ,  Craig E. Hampel ,  Ian Shaeffer ,  Scott C. Best

发明人： Frederick Ware ,  Craig E. Hampel ,  Ian Shaeffer ,  Scott C. Best

IPC分类号： G06F12/00

CPC分类号： G11C7/1072 ,  G06F13/1684 ,  G06F13/4234 ,  G11C5/00

摘要： A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.

摘要翻译： 存储器模块包括其上具有信号线的衬底，其形成控制路径和多个数据路径。 多个存储器件安装在基片上。 每个存储器件耦合到控制路径和不同的数据路径。 存储器模块包括控制电路，以使得每个存储器设备能够在一系列存储器访问命令中处理不同的相应存储器访问命令，并且响应于处理的存储器访问命令在不同的数据路径上输出数据。

公开(公告)号：US08842492B2

公开(公告)日：2014-09-23

申请号：US13823866

申请日：2011-11-19

申请人： Ian Shaeffer ,  Frederick A. Ware ,  Scott C. Best

发明人： Ian Shaeffer ,  Frederick A. Ware ,  Scott C. Best

IPC分类号： G11C8/00 ,  H04L25/40 ,  G06F13/00 ,  G11C7/22

CPC分类号： H04L25/40 ,  G06F13/00 ,  G06F13/1689 ,  G11C7/22 ,  Y02D10/14

摘要： Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal.

摘要翻译： 呈现了在各种实施例中以相同频率循环的多个定时参考信号（例如，时钟信号）以飞越拓扑分布到多个存储器件。 这些多个时钟信号各自具有彼此不同的相位关系（例如，正交）。 第一电路接收这些时钟中的第一个作为第一定时参考信号。 第二电路接收这些时钟中的第二时钟作为第二定时参考信号。 多个接收器电路相对于第一定时参考信号和第二定时参考信号同步地接收信号，使得使用第一定时参考信号来解析第一信号值，并且使用第二定时参考信号来解析第二信号值 。

公开(公告)号：US20130208818A1

公开(公告)日：2013-08-15

申请号：US13823866

申请日：2011-11-19

申请人： Ian Shaeffer ,  Frederick A. Ware ,  Scott C. Best

发明人： Ian Shaeffer ,  Frederick A. Ware ,  Scott C. Best

IPC分类号： H04L25/40

CPC分类号： H04L25/40 ,  G06F13/00 ,  G06F13/1689 ,  G11C7/22 ,  Y02D10/14

摘要： Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal.

摘要翻译： 呈现了在各种实施例中以相同频率循环的多个定时参考信号（例如，时钟信号）以飞越拓扑分布到多个存储器件。 这些多个时钟信号各自具有彼此不同的相位关系（例如，正交）。 第一电路接收这些时钟中的第一个作为第一定时参考信号。 第二电路接收这些时钟中的第二时钟作为第二定时参考信号。 多个接收器电路相对于第一定时参考信号和第二定时参考信号同步地接收信号，使得使用第一定时参考信号来解析第一信号值，并且使用第二定时参考信号来解析第二信号值 。

公开(公告)号：US08060665B2

公开(公告)日：2011-11-15

申请号：US12138383

申请日：2008-06-12

申请人： Craig E. Hampel ,  Scott C. Best

发明人： Craig E. Hampel ,  Scott C. Best

IPC分类号： G06K9/36 ,  G06F1/04 ,  H04L7/02

CPC分类号： H05K1/0248 ,  H05K1/0216 ,  H05K1/0268 ,  H05K2201/09781 ,  H05K2201/10689

摘要： An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/output interface uses empirical information of signal traces coupled to the integrated circuit to adjust a transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. In one embodiment, values representative of the empirical information are stored for use by the integrated circuit to generate trace-specific signals so as to compensate for delay differences that are at least partially caused by unmatched signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths.

摘要翻译： 公开了具有经验确定的延迟匹配的集成电路输入/输出接口。 在一个实施例中，集成电路输入/输出接口使用耦合到集成电路的信号迹线的经验信息来调整接口的每个引脚的发送/接收时钟，以补偿由信号迹线长度差引起的延迟失配。 在一个实施例中，代表经验信息的值被存储供集成电路使用以产生跟踪特定信号，以补偿至少部分地由不匹配的信号迹线长度引起的延迟差异。 在一个实施例中，经验信息包括每个信号迹线的信号飞行时间，其可以从已知信号迹线长度预先测量或预先计算。 在另一个实施例中，经验信息包括从预先计算的或预先测量的信号飞行时间或信号迹线长度计算出的特征相位偏移值。

公开(公告)号：US07398333B2

公开(公告)日：2008-07-08

申请号：US10899719

申请日：2004-07-21

申请人： Craig E. Hampel ,  Scott C. Best

发明人： Craig E. Hampel ,  Scott C. Best

IPC分类号： G06K9/36 ,  G06F1/04 ,  H04L7/02

CPC分类号： H05K1/0248 ,  H05K1/0216 ,  H05K1/0268 ,  H05K2201/09781 ,  H05K2201/10689

摘要： An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/output interface uses empirical information of the signal traces to adjust the transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths. In yet another embodiment, a transmitting device generates a set of serially delayed write clocks, which are used to control symbol transmission over signal traces so as to reduce simultaneous switching output noise and ground bound in the transmitting device.

摘要翻译： 公开了具有经验确定的延迟匹配的集成电路输入/输出接口。 在一个实施例中，集成电路输入/输出接口使用信号迹线的经验信息来调整接口的每个引脚的发送/接收时钟，以补偿由信号迹线长度差引起的延迟失配。 在一个实施例中，经验信息包括每个信号迹线的信号飞行时间，其可以从已知信号迹线长度预先测量或预先计算。 在另一个实施例中，经验信息包括从预先计算的或预先测量的信号飞行时间或信号迹线长度计算出的特征相位偏移值。 在另一个实施例中，发送装置产生一组串行延迟的写入时钟，其用于控制​​信号迹线上的符号传输，以便减少发送装置中同时的开关输出噪声和接地限制。

公开(公告)号：US20080250263A1

公开(公告)日：2008-10-09

申请号：US12138383

申请日：2008-06-12

申请人： Craig E. Hampel ,  Scott C. Best

发明人： Craig E. Hampel ,  Scott C. Best

IPC分类号： G06F1/12

CPC分类号： H05K1/0248 ,  H05K1/0216 ,  H05K1/0268 ,  H05K2201/09781 ,  H05K2201/10689

摘要： An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/output interface uses empirical information of signal traces coupled to the integrated circuit to adjust a transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. In one embodiment, values representative of the empirical information are stored for use by the integrated circuit to generate trace-specific signals so as to compensate for delay differences that are at least partially caused by unmatched signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths.

摘要翻译： 公开了具有经验确定的延迟匹配的集成电路输入/输出接口。 在一个实施例中，集成电路输入/输出接口使用耦合到集成电路的信号迹线的经验信息来调整接口的每个引脚的发送/接收时钟，以补偿由信号迹线长度差引起的延迟失配。 在一个实施例中，代表经验信息的值被存储供集成电路使用以产生跟踪特定信号，以补偿至少部分地由不匹配的信号迹线长度引起的延迟差异。 在一个实施例中，经验信息包括每个信号迹线的信号飞行时间，其可以从已知信号迹线长度预先测量或预先计算。 在另一个实施例中，经验信息包括从预先计算的或预先测量的信号飞行时间或信号迹线长度计算出的特征相位偏移值。

公开(公告)号：US20120311251A1

公开(公告)日：2012-12-06

申请号：US13577838

申请日：2010-12-01

申请人： Scott C. Best ,  Ian Shaeffer

发明人： Scott C. Best ,  Ian Shaeffer

IPC分类号： G06F12/00

CPC分类号： G06F13/1689 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  Y02D10/14

摘要： A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

摘要翻译： 存储器系统包括耦合到多个存储器件的存储器控​​制器。 每个存储器件包括产生内部参考信号的振荡器，该内部参考信号以存储器件内的物理器件结构的函数的频率振荡。 因此，内部参考信号的频率是器件特定的。 每个存储器件从其内部参考信号产生共享参考信号，并将共享参考信号传送到公共存储器控制器。 存储器控制器使用共享参考信号从每个存储器件恢复器件特定的频率信息，然后以与相应的内部参考信号兼容的频率与每个存储器件通信。

公开(公告)号：US09384152B2

公开(公告)日：2016-07-05

申请号：US13577838

申请日：2010-12-01

申请人： Scott C. Best ,  Ian Shaeffer

发明人： Scott C. Best ,  Ian Shaeffer

IPC分类号： G06F13/16

CPC分类号： G06F13/1689 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  Y02D10/14

摘要： A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

摘要翻译： 存储器系统包括耦合到多个存储器件的存储器控​​制器。 每个存储器件包括产生内部参考信号的振荡器，该内部参考信号以存储器件内的物理器件结构的函数的频率振荡。 因此，内部参考信号的频率是器件特定的。 每个存储器件从其内部参考信号产生共享参考信号，并将共享参考信号传送到公共存储器控制器。 存储器控制器使用共享参考信号从每个存储器件恢复器件特定的频率信息，然后以与相应的内部参考信号兼容的频率与每个存储器件通信。