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    Method to form an embedded flash memory circuit with reduced process steps
    3.
    发明授权
    Method to form an embedded flash memory circuit with reduced process steps 有权
    用减少工艺步骤形成嵌入式闪存电路的方法

    公开(公告)号：US06380031B1

    公开(公告)日：2002-04-30

    申请号：US09637090

    申请日：2000-08-10

    申请人： Freidoon Mehrad ,  Jie Xia ,  Sandra Zheng ,  Lancy Tsung

    发明人： Freidoon Mehrad ,  Jie Xia ,  Sandra Zheng ,  Lancy Tsung

    IPC分类号： H01L21336

    CPC分类号： H01L27/11521 ,  H01L29/66825

    摘要： A method to form an embedded FLASH integrated circuit with reduced processing steps is described. In the method a partial etch is performed on the control gate region of a polycrystalline silicon film (21). A multiple etch process is then used to simultaneously form the FLASH memory cell gate stack (54), the NMOS gate structure (94) and the PMOS gate structure (96).

    摘要翻译： 描述了一种以缩短处理步骤形成嵌入式FLASH集成电路的方法。 在该方法中，对多晶硅膜（21）的控制栅极区域进行部分蚀刻。 然后使用多重蚀刻工艺同时形成闪存存储单元栅极堆叠（54），NMOS栅极结构（94）和PMOS栅极结构（96）。

    Method to reduce source-line resistance in flash memory with sti
    4.
    发明授权
    Method to reduce source-line resistance in flash memory with sti 有权
    减少闪存中源线电阻的方法

    公开(公告)号：US06306737B1

    公开(公告)日：2001-10-23

    申请号：US09492571

    申请日：2000-01-27

    申请人： Freidoon Mehrad ,  Thomas M. Ambrose ,  Lancy Y. Tsung

    发明人： Freidoon Mehrad ,  Thomas M. Ambrose ,  Lancy Y. Tsung

    IPC分类号： H01L21425

    CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

    摘要： A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72). The method involves forming steps (104) in the sidewalls of the trench (72) in a semiconductor substrate (52). A dopant may be implanted at a first energy level into the semiconductor substrate (52) to form a first conductive region (92). The dopant may be implanted at a second energy level into the semiconductor substrate (52) to form a second conductive region (94). The first energy level may be greater than the second energy level. The first conductive region (92) and the second conductive region (94) may form the conductive line (24).

    摘要翻译： 一种形成具有穿过沟槽（72）的导电线（24）的半导体部件的方法。 该方法包括在半导体衬底（52）中的沟槽（72）的侧壁中形成步骤（104）。 掺杂剂可以以第一能级注入到半导体衬底（52）中以形成第一导电区域（92）。 掺杂剂可以以第二能级注入到半导体衬底（52）中以形成第二导电区域（94）。 第一能级可能大于第二能级。 第一导电区域（92）和第二导电区域（94）可以形成导线（24）。

    GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM
    6.
    发明申请
    GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM 有权
    门式电介质第一次更换门电路及集成电路

    公开(公告)号：US20110031557A1

    公开(公告)日：2011-02-10

    申请号：US12908140

    申请日：2010-10-20

    申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

    发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

    摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

    摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

    PROCESS METHOD TO FULLY SALICIDE (FUSI) BOTH N-POLY AND P-POLY ON A CMOS FLOW
    8.
    发明申请
    PROCESS METHOD TO FULLY SALICIDE (FUSI) BOTH N-POLY AND P-POLY ON A CMOS FLOW 有权
    在CMOS流程上充分浸出（FUSI）N-POLY和P-POLY的方法

    公开(公告)号：US20090050976A1

    公开(公告)日：2009-02-26

    申请号：US11844832

    申请日：2007-08-24

    申请人： Freidoon Mehrad ,  Frank S. Johnson

    发明人： Freidoon Mehrad ,  Frank S. Johnson

    IPC分类号： H01L21/3205 ,  H01L29/78

    CPC分类号： H01L21/823835

    摘要： An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming a first silicide in at least a top portion of a gate electrode of the PMOS devices and not over the NMOS devices. The method further comprises concurrently forming a second silicide in at least a top portion of a gate electrode of both the NMOS and PMOS devices, and forming a FUSI gate silicide of the gate electrodes. In one embodiment, the thickness of the second silicide is greater than the first silicide by an amount which compensates for a difference in the rates of silicide formation between the NMOS and PMOS devices.

    摘要翻译： 公开了在相同MOS器件的NMOS和PMOS晶体管中形成完全硅化（FUSI）栅极的改进方法。 在一个示例中，该方法包括在PMOS器件的栅电极的至少顶部部分中形成第一硅化物，而不是在NMOS器件上形成。 该方法还包括在NMOS和PMOS器件的栅电极的至少顶部中同时形成第二硅化物，以及形成栅电极的FUSI栅极硅化物。 在一个实施例中，第二硅化物的厚度大于第一硅化物的量，该量补偿了NMOS和PMOS器件之间的硅化物形成速率的差异。

    Process method to facilitate silicidation
    9.
    发明授权
    Process method to facilitate silicidation 有权
    硅化方法

    公开(公告)号：US07448395B2

    公开(公告)日：2008-11-11

    申请号：US10894374

    申请日：2004-07-19

    申请人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

    发明人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

    IPC分类号： B08B6/00 ,  C25F1/00 ,  C25F3/30 ,  C25F5/00

    CPC分类号： H01L21/28518 ,  H01L21/02046 ,  H01L21/0206 ,  H01L21/28052 ,  H01L29/665

    摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.

    摘要翻译： 本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。 随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。 残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。 通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。 第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。 延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

    METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE
    10.
    发明申请
    METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE 有权
    同时硅化多晶硅栅极和半导体器件的源极/漏极的方法及相关器件

    公开(公告)号：US20080265344A1

    公开(公告)日：2008-10-30

    申请号：US11741519

    申请日：2007-04-27

    申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

    发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

    摘要翻译： 同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层 所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及 活跃区域。